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IBM0165165BT3C-50 参数 Datasheet PDF下载

IBM0165165BT3C-50图片预览
型号: IBM0165165BT3C-50
PDF下载: 下载PDF文件 查看货源
内容描述: [EDO DRAM, 4MX16, 50ns, CMOS, PDSO50, 0.400 X 0.825 INCH, PLASTIC, TSOP-50]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 31 页 / 350 K
品牌: IBM [ IBM ]
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IBM0165165B  
IBM0165165P  
4M x 16 12/10 EDO DRAM  
ADVANCED  
Read Cycle  
-50  
-60  
Symbol  
Parameter  
Access Time from RAS  
Units  
Notes  
Min.  
Max.  
50  
Min.  
Max.  
60  
tRAC  
tCAC  
tAA  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1, 2, 3, 5  
1, 2, 5  
1, 2, 5  
1, 5  
Access Time from CAS  
0
13  
25  
13  
13  
13  
0
15  
30  
15  
15  
15  
Access Time from Address  
tOEA  
tRCS  
tRCH  
tRRH  
tRAL  
tCLZ  
tOEZ  
tCDD  
tOFF  
tOES  
tORD  
Access Time From OE  
Read Command Setup Time  
Read Command Hold Time to CAS  
Read Command Hold Time to RAS  
Column Address to RAS Lead Time  
CAS to Output in Low-Z  
0
0
6
0
0
25  
0
30  
0
1
5
7
4
7
Output Buffer Turn-Off Delay From OE  
CAS to DIN Delay Time  
0
0
13  
0
15  
0
Output Buffer Turn-Off Delay  
OE Setup Time Prior to CAS  
OE Setup Time Prior to RAS (Hidden Refresh)  
5
5
0
0
1. In a Test Mode Read cycle, the value of tRAC, tAA, tCAC and tCPA are delayed by 5ns from the specified value. These parameters  
must be adjusted in Test Mode cycles by adding 5ns to the specified value. Associated timings must also be adjusted by 5ns.  
2. Operation within the tRCD(max.) limit ensures that tRAC(max.) can be met. tRCD(max.) is specified as a reference point only. If tRCD  
is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC  
.
3. Operation within the tRAD(max.) limit ensures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only. If tRAD is  
greater than the specified tRAD(max.) limit, then access time is controlled by tAA  
.
4. Either tCDD or tODD must be satisfied.  
5. Measured with the specified current load and 100pF.  
6. Either tRCH or tRRH must be satisfied for a read cycle.  
7. tOFF(max.) and tOEZ(max.) define the time at which the output achieves the open circuit condition and are not referenced to output  
voltage levels.  
©IBM Corporation.. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
27H6253  
SA14-4239-02  
10/96  
Page 8 of 31  
 
 
 
 
 
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