IBM0165165B
IBM0165165P
ADVANCED
4M x 16 12/10 EDO DRAM
DC Electrical Characteristics (TA = 0 to +70°C, VCC = 3.3 ± 0.3V)
Symbol
Parameter
Min.
—
Max.
140
115
Units
mA
Notes
1, 2, 3
Operating Current
-50
-60
ICC1
Average Power Supply Operating Current
(RAS, CAS, Address Cycling: tRC = tRC min)
—
Standby Current (LVTTL)
Power Supply Standby Current
(RAS = CAS = VIH)
ICC2
ICC3
ICC4
—
2
mA
mA
mA
µA
RAS Only Refresh Current
Average Power Supply Current, RAS Only Mode
(RAS Cycling, CAS = VIH: tRC = tRC min)
-50
-60
-50
-60
140
115
105
85
1, 3
—
—
—
EDO (Hyper Page) Mode Current
Average Power Supply Current, Hyper Page Mode
(RAS = VIL, CAS, Address Cycling: tPC = tPC min)
1, 2, 3
Standby Current (LVCMOS)- Low Power
Power Supply Standby Current
(RAS = CAS = VCC - 0.2V)
—
—
200
1
ICC5
Standby Current (LVCMOS)- Standard Power
Power Supply Standby Current
(RAS = CAS = VCC - 0.2V)
mA
mA
CAS Before RAS Refresh Current
Average Power Supply Current, CAS Before RAS Mode
(RAS, CAS, Cycling: tRC = tRC min)
-50
-60
—
—
140
115
ICC6
ICC7
II(L)
1, 2
Self Refresh Current (LP version only)
Average Power Supply Current during Self Refresh
CBR cycle with RAS ≥ tRASS (min); CAS held low;
WE = VCC - 0.2V; Addresses and DIN = VCC - 0.2V or 0.2V.
µA
µA
—
-2
400
+2
Input Leakage Current
Input Leakage Current, any input
(0.0 ≥ VIN ≥ VCC), All Other Pins Not Under Test = 0V
Output Leakage Current
(DOUT is disabled, 0.0 ≥ VOUT ≥ VCC
IO(L)
VOH
VOL
VOH
VOL
µA
V
-2
2.4
+2
—
)
Output High Level (LVTTL)
Output “H” Level Voltage (IOUT = -2mA)
Output Low Level (LVTTL)
Output “L” Level Voltage (IOUT = +2mA)
—
0.4
—
V
Output High Level (LVCMOS)
Output “H” Level Voltage (IOUT = -100µA)
V
CC - 0.2
V
4
4
Output Low Level (LVCMOS)
Output “L” Level Voltage (IOUT = +100µA)
—
0.2
V
1. ICC1, ICC3, ICC4, ICC6 depend on cycle rate.
2. ICC1, ICC4 depend on output loading. Specified values are obtained with the output open.
3. Column address can be changed once or less while RAS =VIL and CAS =VIH.
4. VOL (LVCMOS) and VOH (LVCMOS) levels are not intended for use as timing reference levels. LVCMOS levels are the quiescent
state of a low impedance output driver, under the specified load condition.
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
27H6253
SA14-4239-02
10/96
Page 5 of 31
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