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IBM0165165BT3C-50 参数 Datasheet PDF下载

IBM0165165BT3C-50图片预览
型号: IBM0165165BT3C-50
PDF下载: 下载PDF文件 查看货源
内容描述: [EDO DRAM, 4MX16, 50ns, CMOS, PDSO50, 0.400 X 0.825 INCH, PLASTIC, TSOP-50]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 31 页 / 350 K
品牌: IBM [ IBM ]
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IBM0165165B  
IBM0165165P  
4M x 16 12/10 EDO DRAM  
ADVANCED  
AC Characteristics (TA=0 to +70°C, VCC=3.3 ± 0.3V)  
1. An initial pause of 100µs is required after power-up followed by 8 RAS only refresh cycles before proper device operation is  
achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only refresh  
cycles is required.  
2. AC measurements assume tT=2ns.  
3. VIH(min.) and VIL(max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH  
and VIL.  
4. Valid column addresses are only A0 through A9.  
Read, Write, Read-Modify-Write and Refresh Cycle (Common Parameters)  
-50  
-60  
Symbol  
Parameter  
Units  
Notes  
1
Min.  
84  
30  
8
Max.  
Min.  
104  
40  
10  
60  
10  
0
Max.  
tRC  
tRP  
Random Read or Write Cycle Time  
RAS Precharge Time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCP  
CAS Precharge Time  
tRAS  
tCAS  
tASR  
tRAH  
tASC  
tCAH  
tRCD  
tRAD  
tRSH  
tCSH  
tCRP  
tOED  
tDZO  
tDZC  
tT  
RAS Pulse Width  
50  
8
100k  
100k  
100k  
100k  
1
1
CAS Pulse Width  
Row Address Setup Time  
Row Address Hold Time  
Column Address Setup Time  
Column Address Hold Time  
RAS to CAS Delay Time  
RAS to Col. Address Delay Time  
RAS Hold Time  
0
7
10  
0
0
7
10  
14  
12  
10  
50  
5
11  
9
37  
25  
45  
30  
2
3
8
CAS Hold Time  
40  
5
1
1
4
5
5
6
CAS to RAS Precharge Time  
OE to DIN Delay Time  
13  
0
15  
0
OE Delay Time From DIN  
CAS Delay Time From DIN  
Transition Time (Rise and Fall)  
0
0
1
50  
1
50  
1. In a Test Mode Read cycle, the value of tRAC, tAA, tCAC and tCPA are delayed by 5ns from the specified value. These parameters  
must be adjusted in Test Mode cycles by adding 5ns to the specified value. Associated timings must also be adjusted by 5ns.  
2. Operation within the tRCD(max.) limit ensures that tRAC(max.) can be met. tRCD(max.) is specified as a reference point only. If tRCD  
is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC  
.
3. Operation within the tRAD(max.) limit ensures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only. If tRAD is  
greater than the specified tRAD(max.) limit, then access time is controlled by tAA  
.
4. Either tCDD or tODD must be satisfied.  
5. Either tDZC or tDZO must be satisfied.  
6. AC measurements assume tT = 2ns.  
©IBM Corporation.. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
27H6253  
SA14-4239-02  
10/96  
Page 6 of 31  
 
 
 
 
 
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