1HY5DU561622FTP-5
HY5DU561622FTP-4
4
5
Unit
Note
Parameter
Symbol
Min
0.4
0.9
0.4
0
Max
Min
0.4
0.9
0.4
0
Max
Data-In Hold Time to DQS-In (DQ & DM)
Read DQS Preamble Time
tDH
-
1.1
0.6
-
-
1.1
0.6
-
ns
CK
CK
ns
3
tRPRE
tRPST
tWPRES
tWPREH
tWPST
tMRD
Read DQS Postamble Time
Write DQS Preamble Setup Time
Write DQS Preamble Hold Time
Write DQS Postamble Time
Mode Register Set Delay
1.5
0.4
2
-
1.5
0.4
2
-
ns
0.6
-
0.6
-
CK
CK
CK
Exit Self Refresh to Any Execute Command
Except Read
tXSC
200
-
200
-
4
1tCK
+ tIS
1tCK
+ tIS
tPDEX
-
-
CK
Command
Power Down Exit Time
2tCK
2tCK
Read Command
tPDEX_RD
tREFI
-
-
CK
us
+ tIS
+ tIS
Average Periodic Refresh Interval
-
7.8
-
7.8
Note :
1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.
4. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
5. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).
6. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of
tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects, and p-channel to
n-channel variation of the output drivers.
7. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.
Signal transitions through the DC region must be monotonic.
Rev. 1.1 / Mar. 2008
25
HYNIX [ HYNIX SEMICONDUCTOR ]
