1HY5DU561622FTP-5
HY5DU561622FTP-4
AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)
4
5
Unit
Note
Parameter
Symbol
Min
Max
Min
Max
Row Cycle Time
(Manual Precharge)
tRC
15
-
12
-
CK
CK
Row Cycle Time
(Auto Precharge)
tRC_APCG
17
-
14
-
Auto Refresh Row Cycle Time
Row Active Time
tRFC
18
40
5
-
14
40
4
-
CK
ns
tRAS
70K
70K
tRCDRD
tRCDWT
tRRD
-
-
-
-
-
-
-
-
-
-
CK
CK
CK
CK
CK
Row Address to Column Address Delay
2
2
Row Active to Row Active Delay
Column Address to Column Address Delay
Row Precharge Time
2
2
tCCD
1
1
tRP
5
4
Last Data-In to Precharge Delay
(Write Recovery Time : tWR)
tDPL
tDRL
tDAL
4
2
9
-
-
-
3
2
7
-
-
-
CK
CK
CK
Last Data-In to Read Command
Auto Precharge Write Recovery +
Time
Precharge
CL = 4.0
CL = 3.0
4.0
-
7.0
-
-
-
ns
ns
CK
CK
ns
ns
ns
System Clock Cycle Time
tCK
5.0
0.45
0.45
-0.7
-0.7
-
7.0
Clock High Level Width
tCH
0.45
0.45
-0.7
-0.7
-
0.55
0.55
0.7
0.7
0.4
0.55
0.55
0.7
Clock Low Level Width
tCL
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
tAC
tDQSCK
tDQSQ
0.7
DQS-Out edge to Data-Out edge Skew
Data-Out hold time from DQS
0.45
tHPmin
-tQHS
tHPmin
-tQHS
tQH
tHP
-
-
-
-
ns
ns
1, 6
1, 5
tCH/L
min
tCH/L
min
Clock Half Period
Data Hold Skew Factor
tQHS
tIS
-
0.4
-
-
0.5
-
ns
ns
ns
CK
CK
CK
ns
6
2
2
Input Setup Time
0.75
0.75
0.4
0.75
0.75
0.4
Input Hold Time
tIH
-
-
Write DQS High Level Width
Write DQS Low Level Width
Clock to First Rising edge of DQS-In
Data-In Setup Time to DQS-In (DQ & DM)
tDQSH
tDQSL
tDQSS
tDS
0.6
0.6
1.15
-
0.6
0.6
1.25
-
0.4
0.4
0.85
0.4
0.75
0.4
3
Rev. 1.1 / Mar. 2008
24
HYNIX [ HYNIX SEMICONDUCTOR ]
