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Synchronous DRAM Memory 256Mbit
HY57V561620F(L)T(P) Series
FUNCTIONAL BLOCK DIAGRAM
4Mbit x 4banks x 16 I/O Synchronous DRAM
Self refresh
logic & timer
Internal Row
Counter
CLK
CKE
CS
RAS
CAS
WE
LDQM,
UDQM
State Machine
Row Active
Row
Pre
Decoder
X Decorders
4M x16 Bank3
4M x16 Bank2
4M x16 Bank1
4M x16 Bank0
X Decorders
DQ0
I/O Buffer & Logic
Sense AMP & I/O Gate
X Decorders
X Decoders
Refresh
Column
Active
Memory
Cell
Array
Column
Pre
Decoder
Y decoerders
DQ15
Bank Select
Column Add
Counter
A0
A1
Address Buffers
Address
Register
Burst
Length
Burst
Counter
Pipe Line
Control
A12
BA1
BA0
Mode Register
CAS Latency
Data Out Control
Rev 1.2 / Dec. 2009
8