111
Synchronous DRAM Memory 256Mbit
HY57V561620F(L)T(P) Series
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
5
6
H
Parameter
Symbol
Unit
Note
Min
55
55
15
38.7
15
10
1
Max
Min
60
60
18
42
18
12
1
Max
Min
63
63
20
42
20
15
1
Max
Operation
Auto Refresh
tRC
-
-
-
ns
ns
RAS Cycle Time
tRRC
tRCD
tRAS
tRP
-
-
-
RAS to CAS Delay
RAS Active Time
-
-
-
ns
100K
100K
100K
ns
RAS Precharge Time
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
RAS to RAS Bank Active Delay
CAS to CAS Delay
tRRD
tCCD
tWTL
tDPL
tDAL
tDQZ
tDQM
tMRD
tPROZ3
tPROZ2
tDPE
tSRE
tREF
ns
CLK
CLK
CLK
Write Command to Data-In Delay
Data-in to Precharge Command
Data-In to Active Command
DQM to Data-Out Hi-Z
0
0
0
2
2
2
tDPL + tRP
2
0
2
3
2
1
1
-
-
-
2
0
2
3
2
1
1
-
-
-
2
0
2
3
2
1
1
-
-
-
CLK
CLK
CLK
CLK
CLK
CLK
CLK
ms
DQM to Data-In Mask
MRS to New Command
-
-
-
CL = 3
-
-
-
Precharge to Data
Output High-Z
CL = 2
-
-
-
Power Down Exit Time
Self Refresh Exit Time
Refresh Time
-
-
-
-
-
-
1
64
64
64
Note: 1. A new command can be given tRC after self refresh exit.
Rev 1.2 / Dec. 2009
13
HYNIX [ HYNIX SEMICONDUCTOR ]
