HY57V283220(L)T(P) / HY5V22(L)F(P)
Ball CONFIGURATION ( HY5V22(L)F(P) Series)
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
DQ26
DQ28
VSSQ
VSSQ
VDDQ
VSS
DQ24
VDDQ
DQ27
DQ29
DQ31
DQM3
A5
VSS
VSSQ
DQ25
DQ30
NC
VDD
VDDQ
DQ22
DQ17
NC
DQ23
VSSQ
DQ20
DQ18
DQ16
DQM2
A0
DQ21
DQ19
VDDQ
VDDQ
VSSQ
VDD
A3
A2
G
H
J
A4
A6
A10
A1
Top View
A7
A8
NC
NC
BA1
A11
CLK
CKE
NC
A9
BA0
/CAS
/CS
/RAS
DQM0
K
L
DQM1
NC
/WE
VDDQ
VSSQ
VSSQ
DQ11
DQ13
DQ8
DQ10
DQ12
VDDQ
DQ15
VSS
DQ9
VDD
DQ6
DQ7
DQ5
VSSQ
VDDQ
VDDQ
DQ4
M
N
P
R
DQ14
VSSQ
VSS
DQ1
DQ3
VDDQ
VDD
VSSQ
DQ0
DQ2
Ball DESCRIPTION
PIN
PIN NAME
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the rising edge
of CLK.
CLK
Clock
Controls internal clock signal and when deactivated, the SDRAM will be one of the states
among power down, suspend or self refresh
CKE
Clock Enable
Chip Select
CS
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
BA0, BA1
Bank Address
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
A0 ~ A11
Address
Row Address Strobe,
Column Address Strobe, Write
Enable
RAS, CAS and WE define the operation
Refer function truth table for details
RAS, CAS, WE
DQM0~3
DQ0 ~ DQ31
VDD/VSS
VDDQ/VSSQ
NC
Data Input/Output Mask
Data Input/Output
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power Supply/Ground
Data Output Power/Ground
No Connection
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
Rev. 0.9 / July 2004
4
HYNIX [ HYNIX SEMICONDUCTOR ]
