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HY57V283220T-7 参数 Datasheet PDF下载

HY57V283220T-7图片预览
型号: HY57V283220T-7
PDF下载: 下载PDF文件 查看货源
内容描述: 4银行X 1M X 32位同步DRAM [4 Banks x 1M x 32Bit Synchronous DRAM]
分类和应用: 动态存储器
文件页数/大小: 15 页 / 914 K
品牌: HYNIX [ HYNIX SEMICONDUCTOR ]
 浏览型号HY57V283220T-7的Datasheet PDF文件第5页浏览型号HY57V283220T-7的Datasheet PDF文件第6页浏览型号HY57V283220T-7的Datasheet PDF文件第7页浏览型号HY57V283220T-7的Datasheet PDF文件第8页浏览型号HY57V283220T-7的Datasheet PDF文件第10页浏览型号HY57V283220T-7的Datasheet PDF文件第11页浏览型号HY57V283220T-7的Datasheet PDF文件第12页浏览型号HY57V283220T-7的Datasheet PDF文件第13页  
HY57V283220(L)T(P) / HY5V22(L)F(P)  
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)  
-5  
-55  
-6  
-7  
-H  
-8  
-P  
-S  
Parameter  
Symbol  
Unit Note  
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max  
CAS Latency = 3  
tCK3  
tCK2  
tCHW  
tCLW  
tAC3  
tAC2  
tOH  
5
10  
2
5.5  
10  
2.25  
2.25  
-
6
10  
2.5  
2.5  
-
7
7.5  
8
-10  
3
3
-
10  
10  
3
3
-
10  
12  
3
3
-
ns  
ns  
System clock  
cycle time  
1000  
1000  
1000  
1000  
1000  
1000  
1000  
1000  
CAS Latency = 2  
10  
10  
Clock high pulse width  
Clock low pulse width  
-
-
-
-
-
-
3
-
-
3
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1
1
2
3
3
CAS Latency = 3  
-
4.5  
6
-
5
6
-
5.5  
6
-
-
5.5  
6
-
-
5.5  
6
-
6
6
-
6
6
-
6
6
-
Access time from  
clock  
2
CAS Latency = 2  
-
-
-
-
-
-
-
-
Data-out hold time  
1.5  
1.5  
1
2
2
2
1.75  
1
2
1.75  
1
2
2
1
2
1
2
1
2
1
1
-
2
2
1
2
1
2
1
2
1
1
-
2
2
1
2
1
2
1
2
1
1
-
3
1
1
1
1
1
1
1
1
Data-Input setup time  
Data-Input hold time  
Address setup time  
Address hold time  
tDS  
-
1.5  
1
-
1.5  
1
-
-
-
-
-
-
tDH  
-
-
-
-
-
-
-
-
tAS  
1.5  
1
-
1.5  
1
-
1.5  
1
-
1.75  
1
-
1.75  
1
-
-
-
-
tAH  
-
-
-
-
-
-
-
-
CKE setup time  
tCKS  
tCKH  
tCS  
1.5  
1
-
1.5  
1
-
1.5  
1
-
1.75  
1
-
1.75  
1
-
-
-
-
CKE hold time  
-
-
-
-
-
-
-
-
Command setup time  
Command hold time  
CLK to data output in low Z-time  
1.5  
1
-
1.5  
1
-
1.5  
1
-
1.75  
1
-
1.75  
1
-
-
-
-
tCH  
-
-
-
-
-
-
-
-
tOLZ  
tOHZ3  
tOHZ2  
1
-
1
-
1
-
1
-
1
-
-
-
-
CAS Latency = 3  
-
4.5  
6
-
5
6
-
5.5  
6
-
5.5  
6
-
5.5  
6
6
6
6
6
6
6
CLK to data output  
in high Z-time  
CAS Latency = 2  
-
-
-
-
-
-
-
-
Note :  
1.Assume tR / tF (input rise and fall time ) is 1ns  
2.Access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v  
3.Data-out hold time to be measured under 30pF load condition, without Vt termination  
Rev. 0.9 / July 2004  
9