HY57V283220(L)T(P) / HY5V22(L)F(P)
PIN CONFIGURATION ( HY57V283220(L)T(P) Series)
V
D D
8 6
8 5
8 4
8 3
8 2
8 1
8 0
7 9
7 8
7 7
7 6
7 5
7 4
7 3
7 2
7 1
7 0
6 9
6 8
6 7
6 6
6 5
6 4
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6
5 5
5 4
5 3
5 2
5 1
5 0
4 9
4 8
4 7
4 6
4 5
4 4
1
2
3
4
5
6
7
8
V
S S
D Q 1 5
S S Q
V
D Q 1 4
D Q 1 3
D D Q
V
D Q 1 2
D Q 1 1
D Q 0
D D Q
D Q 1
D Q 2
V
V
S S Q
D Q 3
D Q 4
D D Q
D Q 5
D Q 6
V
9
V
S S Q
D Q 1 0
D Q 9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 8
3 9
4 0
4 1
4 2
4 3
V
S S Q
D D Q
V
D Q 7
N C
D D
D Q 8
N C
V
S S
V
D Q M 0
/W E
/C A S
/R A S
/C S
A 1 1
B A 0
B A 1
A 1 0 /A P
A 0
A 1
A 2
D Q M 2
D Q M 1
N C
N C
C L K
C K E
A 9
A 8
A 7
A 6
A 5
8 6 p in T S O P II
4 0 0 m il x 8 7 5 m il
0 .5 m m p in p itc h
A 4
A 3
D Q M 3
V
D D
S S
V
N C
D Q 1 6
S S Q
N C
D Q 3 1
V
V
D D Q
D Q 1 7
D Q 1 8
D D Q
D Q 3 0
D Q 2 9
V
V
S S Q
D Q 1 9
D Q 2 0
S S Q
D Q 2 8
D Q 2 7
V
D D Q
V
D Q 2 1
D Q 2 2
D D Q
D Q 2 3
D D
D Q 2 6
D Q 2 5
V
S S Q
D Q 2 4
S S
V
V
V
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM
on the rising edge of CLK.
CLK
Clock
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
CKE
Clock Enable
Chip Select
CS
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
BA0, BA1
Bank Address
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
A0 ~ A11
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation
Refer function truth table for details
RAS, CAS, WE
DQM0~3
Data Input/Output Mask
Data Input/Output
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
DQ0 ~ DQ31
V
V
DD/VSS
Power Supply/Ground
Power supply for internal circuits and input buffers
Power supply for output buffers
DDQ/VSSQ
Data Output Power/Ground
No Connection
NC
No connection
Rev. 0.9 / July 2004
3
HYNIX [ HYNIX SEMICONDUCTOR ]
