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H5PS1G83EFR 参数 Datasheet PDF下载

H5PS1G83EFR图片预览
型号: H5PS1G83EFR
PDF下载: 下载PDF文件 查看货源
内容描述: 1GB DDR2 SDRAM [1Gb DDR2 SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 44 页 / 566 K
品牌: HYNIX [ HYNIX SEMICONDUCTOR ]
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H5PS1G43EFR  
H5PS1G83EFR  
H5PS1G63EFR  
1.3 PIN DESCRIPTION  
PIN  
TYPE  
DESCRIPTION  
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled  
on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer-  
enced to the crossings of CK and CK (both directions of crossing).  
CK, CK  
Input  
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device  
input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF  
REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is  
synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchro-  
nous for SELF REFRESH exit. After VREF has become stable during the power on and initialization  
sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh  
entry and exit, VREF must be maintained to this input. CKE must be maintained HIGH throughout  
READ and WRITE accesses. Input buffers, excluding CK, CK and CKE are disabled during POWER  
DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH.  
CKE  
CS  
Input  
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external  
bank selection on systems with multiple banks. CS is considered part of the command code.  
Input  
Input  
On Die Termination Control: ODT (registered HIGH) enables on die termination resistance  
internal to the DDR2 SDRAM. When enabled, ODT is only applied to DQ, DQS, DQS, RDQS,  
RDQS, and DM signal for x4,x8 configurations. For x16 configuration ODT is applied to each DQ,  
UDQS/UDQS.LDQS/LDQS, UDM and LDM signal. The ODT pin will be ignored if the Extended  
Mode Register(EMR(1)) is programmed to disable ODT.  
ODT  
RAS, CAS, WE  
Input  
Input  
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.  
Input Data Mask: DM is an input mask signal for write data. Input Data is masked when DM is  
sampled High coincident with that input data during a WRITE access. DM is sampled on both  
edges of DQS, Although DM pins are input only, the DM loading matches the DQ and DQS load-  
ing. For x8 device, the function of DM or RDQS/ RDQS is enabled by EMR command to EMR(1).  
DM  
(LDM, UDM)  
Bank Address Inputs: BA0 - BA2 define to which bank an ACTIVE, Read, Write or PRECHARGE  
command is being applied (For 256Mb and 512Mb, BA2 is not applied). Bank address also deter-  
mines if one of the mode register or extended mode register is to be accessed during a MR or  
EMR command cycle.  
BA0 - BA2  
Input  
Input  
Address Inputs: Provide the row address for ACTIVE commands, and the column address and  
AUTO PRECHARGE bit for READ/WRITE commands to select one location out of the memory  
array in the respective bank. A10 is sampled during a precharge command to determine whether  
the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to  
be precharged, the bank is selected by BA0-BA2. The address inputs also provide the op code  
during MRS or EMRS commands.  
A0 -A15  
DQ  
Input/Output Data input / output: Bi-directional data bus  
Data Strobe: Output with read data, input with write data. Edge aligned with read data, cen-  
tered in write data. For the x16, LDQS correspond to the data on DQ0~DQ7; UDQS corresponds  
to the data on DQ8~DQ15. For the x8, an RDQS option using DM pin can be enabled via the  
EMR(1) to simplify read timing. The data strobes DQS, LDQS, UDQS, and RDQS may be used in  
single ended mode or paired with optional complementary signals DQS, LDQS,UDQS and RDQS  
to provide differential pair signaling to the system during both reads and writes. An EMR(1) con-  
trol bit enables or disables all complementary data strobe signals.  
DQS, (DQS)  
(UDQS),(UDQS)  
(LDQS),(LDQS)  
(RDQS),(RDQS)  
In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMR(1)  
x4 DQS/DQS  
Input/Output  
x8 DQS/DQS  
if EMR(1)[A11] = 0  
if EMR(1)[A11] = 1  
x8 DQS/DQS, RDQS/RDQS,  
x16 LDQS/LDQS and UDQS/UDQS  
"single-ended DQS signals" refers to any of the following with A10 = 1 of  
EMR(1)  
x4 DQS  
x8 DQS  
x8 DQS, RDQS,  
if EMR(1)[A11] = 0  
if EMR(1)[A11] = 1  
x16 LDQS and UDQS  
Rev. 0.4 / Nov 2008  
8