11
1Gbit (32Mx32bit) Mobile SDR Memory
H55S1G(2/3)2MFP Series
FEATURES
●
●
Standard SDRAM Protocol
Clock Synchronization Operation
- All the commands registered on positive edge of basic input clock (CLK)
MULTIBANK OPERATION - Internal 4bank operation
- During burst Read or Write operation, burst Read or Write for a different bank is performed.
- During burst Read or Write operation, a different bank is activated and burst Read or Write
for that bank is performed
●
- During auto precharge burst Read or Write, burst Read or Write for a different bank is performed
Power Supply Voltage : VDD = 1.8V, VDDQ = 1.8V
LVCMOS compatible I/O Interface
●
●
●
●
●
●
●
●
Low Voltage interface to reduce I/O power
Programmable burst length: 1, 2, 4, 8 or full page
Programmable Burst Type : sequential or interleaved
Programmable CAS latency of 2 or 3
Programmable Drive Strength
Low Power Features
- Programmable PASR(Partial Array Self Refresh)
- Auto TCSR (Temperature Compensated Self Refresh)
- Programmable DS (Drive Strength)
- Deep Power Down Mode
●
●
Operation Temperature
- -30oC ~ 85oC
Package Type
- 90 Ball Lead Free FBGA
1Gb SDRAM ORDERING INFORMATION
Page
Size
Part Number
Clock Frequency
Organization
Interface Package
H55S1G32MFP-60
H55S1G32MFP-75
H55S1G32MFP-A3
H55S1G22MFP-60
H55S1G22MFP-75
H55S1G22MFP-A3
166MHz
133MHz
105MHz
166MHz
133MHz
105MHz
2kBytes
4kBytes
4banks x 8Mb x 32
LVCMOS 90 Ball FBGA
Rev 1.2 / Jun. 2008
5
HYNIX [ HYNIX SEMICONDUCTOR ]
