11
1Gbit (32Mx32bit) Mobile SDR Memory
H55S1G(2/3)2MFP Series
Document Title
4Bank x 8M x 32bit Synchronous DRAM
Revision History
Revision No.
History
Draft Date
Remark
0.1
Initial Draft
Sep. 2007
Preliminary
Modify : IDD5 : 100mA --> 120mA
0.2
1.0
1.1
Jan. 2008
Mar. 2008
May 2008
Preliminary
IDD6 (@45oC, Full Bank) : 450uA --> 500uA
Final Version
Modify : IDD6 (@45oC, Full Bank) : 500uA --> 450uA
IDD6 (@85oC, One Bank) : 550uA --> 500uA
1.2
Jun. 2008
Modify : tRAS (166MHz/133Mhz: 42ns/45ns)
Rev 1.2 / Jun. 2008
2