GMS81C5108 APPENDIX
Control Operation & Etc.
Op
Code
Byte
No
Cycle
No
Flag
NVGBHIZC
No.
1
Mnemonic
Operation
Software interrupt : B ← ”1”, M(sp) ← (pc ), sp ←sp-1,
M(s) ← (pc ), sp ← sp - 1, M(sp) ← (PSW), sp ← sp -1,
H
BRK
0F
1
8
---1-0--
L
pc ← ( 0FFDE ) , pc ← ( 0FFDF ) .
L
H
H
H
2
3
DI
EI
60
E0
FF
0D
2D
4D
6D
0E
2E
4E
6E
1
1
1
1
1
1
1
1
1
1
1
3
3
2
4
4
4
4
4
4
4
4
Disable all interrupts : I ← “0”
Enable all interrupt : I ← “1”
No operation
-----0--
-----1--
--------
4
NOP
5
POP A
sp ← sp + 1, A ← M( sp )
sp ← sp + 1, X ← M( sp )
sp ← sp + 1, Y ← M( sp )
sp ← sp + 1, PSW ← M( sp )
M( sp ) ← A , sp ← sp - 1
M( sp ) ← X , sp ← sp - 1
M( sp ) ← Y , sp ← sp - 1
M( sp ) ← PSW , sp ← sp - 1
Return from subroutine
6
POP X
--------
restored
--------
7
POP Y
8
POP PSW
PUSH A
PUSH X
PUSH Y
PUSH PSW
9
10
11
12
13
RET
6F
1
5
--------
sp ← sp +1, pc ← M( sp ), sp ← sp +1, pc ← M( sp )
L
H
Return from interrupt
sp ← sp +1, PSW ← M( sp ), sp ← sp + 1,
14
15
RETI
7F
EF
1
1
6
3
restored
--------
pc ← M( sp ), sp ← sp + 1, pc ← M( sp )
L
H
STOP
Stop mode ( halt CPU, stop oscillator )
x
JUNE 2001 Ver 1.0
HYNIX [ HYNIX SEMICONDUCTOR ]
