GMS82512/16/24
HYUNDAI MicroElectronics
activated mode: rising edge, falling edge, and both edge.
spondingly.
Example:
To use as an INT0 and INT2
:
:
INT0 pin
INT1 pin
INT0IF
;**** Set port as an input port R40,R42
INT0 INTERRUPT
LDM
;
R4DD,#1111_1010B
;**** Set port as an external interrupt port
INT1IF
LDM
;
PMR4,#05H
INT1 INTERRUPT
;**** Set Falling-edge Detection
LDM
:
:
:
IEDS,#0001_0001B
INT2 pin
INT3 pin
INT2IF
INT2 INTERRUPT
Response Time
INT3IF
The INT0 ~ INT3 edge are latched into INT1IF ~ INT3IF
at every machine cycle. The values are not actually polled
by the circuitry until the next machine cycle. If a request is
active and conditions are right for it to be acknowledged, a
hardware subroutine call to the requested service routine
will be the next instruction to be executed. The DIV itself
takes twelve cycles. Thus, a minimum of twelve complete
machine cycles elapse between activation of an external
interrupt request and the beginning of execution of the first
instruction of the service routine.
INT3 INTERRUPT
2
2
2
2
Edge selection
Register
IEDS
[0F8H]
Figure 14-7 External Interrupt Block Diagram
INT0 ~ INT3 are multiplexed with general I/O ports
(R40~R43). To use as an external interrupt pin, the bit of
R4 port mode register PMR4 should be set to “1” corre-
Figure 14-8shows interrupt response timings.
max. 12 f
8 f
XIN
XIN
Interrupt
goes
active
Interrupt
latched
Interrupt
processing
Interrupt
routine
Figure 14-8 Interrupt Response Timing Diagram
52
FEB. 2000 Ver 1.00
HYNIX [ HYNIX SEMICONDUCTOR ]
