GMS82512/16/24
HYUNDAI MicroElectronics
.
Internal bus line
[0F6 ]
H
I-flag is in PSW, it is cleared by “DI”, set by
“EI” instruction. When it goes interrupt service,
I-flag is cleared by hardware, thus any other
Interrupt Enable
Register (Higher byte)
IENH
IRQH
[0F7 ]
H
interrupt are inhibited. When interrupt service is
completed by “RETI” instruction, I-flag is set to
“1” by hardware.
INT0IF
INT1IF
INT2IF
INT3IF
T0IF
INT0
INT1
INT2
INT3
Release STOP
Timer 0
Timer 1
Timer 2
To CPU
T1IF
T2IF
I-flag
Timer 3
T3IF
Interrupt Master
Enable Flag
IRQL
[0F5 ]
H
A/D Converter
Watchdog Timer
BIT
ADIF
WDTIF
BITIF
Interrupt
Vector
Address
Generator
Interrupt Enable
Register (Lower byte)
[0F4 ]
IENL
H
Internal bus line
Figure 14-2 Block Diagram of Interrupt
R/W R/W
R/W R/W R/W R/W R/W R/W
ADDRESS: 0F6
INITIAL VALUE: 0000 0000
H
INT2E
T1E T2E
INT0E INT1E
INT3E T0E
T3E
LSB
IENH
B
MSB
Timer/Counter 3 interrupt enable flag
Timer/Counter 2 interrupt enable flag
Timer/Counter 1 interrupt enable flag
Timer/Counter 0 interrupt enable flag
External interrupt 3 enable flag
External interrupt 2 enable flag
External interrupt 1 enable flag
External interrupt 0 enable flag
VALUE
R/W R/W R/W
ADE WDTE BITE
0: Disable
1: Enable
ADDRESS: 0F4
INITIAL VALUE: 000- ----
H
-
-
-
-
-
IENL
B
MSB
LSB
Basic Interval Timer interrupt enable flag
Watchdog timer interrupt enable flag
A/D Converter interrupt enable flag
Figure 14-3 Interrupt Enable Flag
48
FEB. 2000 Ver 1.00
HYNIX [ HYNIX SEMICONDUCTOR ]
