GMS82512/16/24
HYUNDAI MicroElectronics
15. WATCHDOG TIMER
The watchdog timer rapidly detects the CPU malfunction
such as endless looping caused by noise or the like, and re-
sumes the CPU to the normal state.
When the watchdog timer is not being used for malfunc-
tion detection, it can be used as a timer to generate an in-
terrupt at fixed intervals.
The watchdog timer signal for detecting malfunction can
be selected either a reset CPU or a interrupt request.
clear
Watchdog
Counter (8-bit)
clear
BASIC INTERVAL TIMER
OVERFLOW
Count source
“0”
to reset CPU
“1”
comparator
enable
WDTON in CKCTLR [0D3 ]
H
6-bit compare data
WDTCL
WDTIF
6
Watchdog Timer interrupt
Watchdog Timer
Register
WDTR
[0E0 ]
H
Internal bus line
Figure 15-1 Block Diagram of Watchdog Timer
Watchdog Timer Control
er output will become active at the rising overflow from
the binary counters unless the binary counter is cleared. At
this time, when WDTON=1, a reset is generated, which
drives the RESET pin to low to reset the internal hardware.
When WDTON=0, a watchdog timer interrupt (WDTIF) is
generated.
Figure 15-2 shows the watchdog timer control register.
The watchdog timer is automatically disabled after reset.
The CPU malfunction is detected during setting of the de-
tection time, selecting of output, and clearing of the binary
counter. Clearing the binary counter is repeated within the
detection time.
The watchdog timer temporarily stops counting in the
STOP mode, and when the STOP mode is released, it au-
tomatically restarts (continues counting).
If the malfunction occurs for any cause, the watchdog tim-
W
7
-
W
6
W
5
W
4
W
3
W
2
W
1
W
0
ADDRESS: 0E0
INITIAL VALUE: -011_1111
H
W DTCL
WDTR
B
6-bit compare data
Clear count flag
0: Free-run count
1: When the WDTCL is set to “1”, binary counter
is cleared to “0”. And the WDTCL becomes “0” automatically
after one machine cycle. Counter count up again.
NOTE:
The WDTON bit is in register CKCTLR.
Figure 15-2 WDTR: Watchdog Timer Data Register
54
FEB. 2000 Ver 1.00
HYNIX [ HYNIX SEMICONDUCTOR ]
