GMS82512/16/24
HYUNDAI MicroElectronics
16. POWER DOWN OPERATION
GMS825xx has a power-down mode. In power-down
mode, power consumption is reduced considerably that in
battery operation. Battery life can be extended a lot.
STOP Mode is entered by STOP instruction.
16.1 STOP Mode
For applications where power consumption is a critical
factor, device provides reduced power of STOP.
Note: Since the XIN pin is connected internally to GND to
avoid current leakage due to the crystal oscillator in STOP
mode, do not use STOP instruction when an external clock
is used as the main system clock.
Start The Stop Operation
An instruction that STOP causes to be the last instruction
is executed before going into the STOP mode. In the Stop
mode, the on-chip main-frequency oscillator is stopped.
With the clock frozen, all functions are stopped, but the on-
chip RAM and Control registers are held. The port pins
output the values held by their respective port data register,
the port direction registers. The status of peripherals during
Stop mode is shown below.
In the Stop mode of operation, VDD can be reduced to min-
imize power consumption. Be careful, however, that VDD
is not reduced before the Stop mode is invoked, and that
VDD is restored to its normal operating level before the
Stop mode is terminated.
The reset should not be activated before VDD is restored to
its normal operating level, and must be held active long
enough to allow the oscillator to restart and stabilize.
And after STOP instruction, at least two or more NOP in-
struction should be written as shown in example below.
Peripheral
STOP Mode
CPU
RAM
All CPU operations are disabled
Retain
Low
Example:
XIN PIN
OUT PIN
LDM
STOP
NOP
NOP
:
CKCTLR,#0000_1110B
X
High
Oscillation
Stop
I/O ports
Retain
The Interval Timer Register CKCTLR should be initial-
ized (0FH or 0EH) by software in order that oscillation sta-
bilization time should be longer than 20ms before STOP
mode.
Control Registers
Release method
Retain
by RESET, by External interrupt
Oscillator
(X pin)
IN
Internal Clock
External Interrupt
STOP Instruction
Executed
n
n+1 n+2
n+3
1
BIT Counter
0
0
FE
1
2
FF
Clear
Normal Operation
Stop Operation
Normal Operation
t
> 20ms
ST
by software
Before executing Stop instruction, Basic Interval Timer must be set
properly by software to get stabilization time which is longer than 20ms.
Figure 16-1 STOP Mode Release Timing by External Interrupt
56
FEB. 2000 Ver 1.00
HYNIX [ HYNIX SEMICONDUCTOR ]
