GMS81C1102 / GMS81C1202
A_D4
A_D3
A_D2
A_D1
A_D0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A_D5
A_D6
A_D7
V
V
DD
SS
V
PP
CTL0
CTL1
CTL2
NC
EPROM Enable
Figure 24-2 Pin Assignment
User Mode
Pin Name
EPROM MODE
Pin No.
Pin Name
Description
1
2
RA4 (AN4)
A_D4
A12
A13
A14
A15
A4
A5
A6
A7
D4
D5
D6
D7
RA5 (AN5)
RA6 (AN6)
RA7 (AN7)
A_D5
A_D6
A_D7
Address Input
Data Input/Output
3
4
V
DD
V
DD
Connect to V (6.0V)
5
DD
6
RB0 (AVref/AN0)
RB2 (INT0)
CTL0
CTL1
CTL2
Read/Write Control
Address/Data Control
7
8
RB4 (PWM/COMP)
X
IN
9
EPROM Enable High Active, Latch Address in falling edge
X
10
11
12
13
14
15
16
NC
V
No connection
OUT
RESET
Programming Power (0V, 12.75V)
PP
V
SS
V
SS
Connect to V (0V)
SS
RA0 (EC0)
RA1 (AN1)
RA2 (AN2)
RA3 (AN3)
A_D0
A_D1
A_D2
A_D3
A8
A9
A0
A1
A2
A3
D0
D1
D2
D3
Address Input
Data Input/Output
A10
A11
Table 24-1 Pin Description in EPROM Mode
72
Jan. 2002 ver 2.0
HYNIX [ HYNIX SEMICONDUCTOR ]
