GMS81C1102 / GMS81C1202
THLD1
TSET1
THLD2
TDLY2
TDLY1
EPROM
Enable
TVPPS
VIHP
V
PP
TVPPR
TVDDS
0V
CTL0
CTL1
CTL2
VDD1H
TCD1
VDD1H
TCD1
0V
TCD1
TCD1
0V
A_D7~
A_D0
DATA
OUT
DATA
OUT
HA
LA
LA
DATA IN
DATA IN
VDD1H
V
DD
Write Mode
Low 8bit
Address
Input
Verify
Write Mode
Low 8bit
Address
Input
Verify
High 8bit
Address
Input
Figure 24-4 Timing Diagram in Program (Write & Verify) Mode
After input a high address,
output data following low address input
Anothe high address step
THLD1
TSET1
THLD2
TDLY2
TDLY1
EPROM
Enable
TVPPS
VIHP
V
PP
TVDDS
0V
TVPPR
CTL0
CTL1
CTL2
VDD2H
TCD2
TCD2
0V
0V
VDD2H
TCD1
TCD1
A_D7~
A_D0
HA
LA
LA
DATA
DATA
HA
DATA
LA
VDD2H
V
DD
DATA
Output
DATA
Output
Low 8bit
Address
Input
Low 8bit
Address
Input
Low 8bit
Address
Input
DATA
Output
High 8bit
Address
Input
High 8bit
Address
Input
Figure 24-5 Timing Diagram in READ Mode
74
Jan. 2002 ver 2.0
HYNIX [ HYNIX SEMICONDUCTOR ]
