GMS81C1102 / GMS81C1202
22. RESET
The reset input is the RESET pin, which is the input to a
Schmitt Trigger. A reset in accomplished by holding the
RESET pin low for at least 8 oscillator periods, while the
oscillator running. After reset, 64ms (at 4 MHz) add with
7 oscillator periods are required to start execution as shown
in Figure 22-1 .
Internal RAM is not affected by reset. When VDD is turned
on, the RAM content is indeterminate. Therefore, this
RAM should be initialized before reading or testing it.
Initial state of each register is shown as Table 12-3 .
1
2
3
4
5
6
7
Oscillator
(X pin)
IN
RESET
ADDRESS
BUS
FFFE FFFF Start
?
?
?
?
DATA
BUS
?
OP
ADH
?
?
?
FE
ADL
MAIN PROGRAM
RESET Process Step
Stabilization Time
tST = 64mS at 4MHz
Figure 22-1 Timing Diagram after RESET
68
Jan. 2002 ver 2.0
HYNIX [ HYNIX SEMICONDUCTOR ]
