GMS81C1102 / GMS81C1202
23. POWER FAIL PROCESSOR
The GMS81C1202 has an on-chip power fail detection cir-
cuitry to immunize against power noise. A configuration
register, PFDR, can enable (if clear/programmed) or disa-
ble (if set) the Power-fail Detect circuitry. If VDD falls be-
low 3.0~4.0V range for longer than 50 nS, the Power fail
situation may reset MCU according to PFDM bit of PFDR.
cuit emulator, user can not experiment with it. Therefore,
after final development of user program, this function may
be experimented.
Note: Power fail processor function is not available on 3V
operation, because this function will detect power
fail all the time.
As below PFDR register is not implemented on the in-cir-
Power Fail Detector Register
ADDRESS : EFH
RESET VALUE : -----100
-
-
-
-
PFDR
-
PFDIS
PFDM
PFS
Reserved
Power Fail Status
0 : Normal Operate
1 : This bit force to "1" when
Power fail was detected
Operation Mode
0 : System clock freezing during power fail
1 : MCU will be reset during power fail
Disable Flag
0 : Power fail detection enable
1 : Power fail detection disable
Figure 23-1 Power Fail Detector Register
RESET VECTOR
YES
PFS =1
NO
RAM CLEAR
INITIALIZE RAM DATA
Skip the
initial routine
INITIALIZE ALL PORTS
INITIALIZE REGISTERS
FUNTION
EXECUTION
Figure 23-2 Example S/W of RESET by Power fail
Jan. 2002 ver 2.0
69
HYNIX [ HYNIX SEMICONDUCTOR ]
