GMS81C1102 / GMS81C1202
level (VDD/VSS), however, when the input level gets high-
er than the power voltage level (by approximately 0.3 to
0.5V), a current begins to flow. Therefore, if cutting off the
output transistor at an I/O port puts the pin signal into the
high-impedance state, a current flow across the ports input
transistor, requiring to fix the level by pull-up or other
means.
sinking current, if it is practical. Weak pull-ups on port
pins should be turned off, if possible. All inputs should be
either as VSS or at VDD (or as close to rail as possible).
An intermediate voltage on an input pin causes the input
buffer to draw a significant amount of current.
Release the STOP mode
STOP
INSTRUCTION
The exit from STOP mode is hardware reset or external in-
terrupt. Reset re-defines all the Control registers but does
not change the on-chip RAM. External interrupts allow
both on-chip RAM and Control registers to retain their val-
ues.
STOP Mode
Interrupt Request
After releasing STOP mode, instruction execution is divid-
ed into two ways by I-flag(bit2 of PSW).
If I-flag = 1, the normal interrupt response takes place. If I-
flag = 0, the chip will resume execution starting with the
instruction following the STOP instruction. It will not vec-
tor to interrupt service routine. (refer to Figure 21-1)
=0
Corresponding Interrupt
IEXX
Enable Bit (IENH, IENL)
=1
STOP Mode Release
When exit from Stop mode by external interrupt, enough
oscillation stabilization time is required to normal opera-
tion. Figure 21-2 shows the timing diagram. When release
the Stop mode, the Basic interval timer is activated on
wake-up. It is increased from 00H until FFH. The count
overflow is set to start normal operation. Therefore, before
STOP instruction, user must be set its relevant prescaler di-
vide ratio to have long enough time (more than 20msec).
This guarantees that oscillator has started and stabilized.
=0
Master Interrupt
Enable Bit PSW[2]
I-FLAG
=1
Interrupt Service Routine
Next
INSTRUCTION
By reset, exit from Stop mode is shown in Figure 21-3.
Figure 21-1 STOP Releasing Flow by Interrupts
Minimizing Current Consumption in Stop Mode
The Stop mode is designed to reduce power consumption.
To minimize the current consumption during Stop mode,
the user should turn-off output drivers that are sourcing or
Oscillator
(X pin)
IN
Internal
Clock
External
Interrupt
Clear Basic Interval Timer
STOP Instruction Execution
BIT
Counter
N-1
N
N+1
N+2
N-2
00
01
FE FF 00
01
Normal Operation
Stabilization Time
tST > 20mS
STOP Mode
Normal Operation
Figure 21-2 Timing of STOP Mode Release by External Interrupt
64
Jan. 2002 ver 2.0
HYNIX [ HYNIX SEMICONDUCTOR ]
