GMS81C1102 / GMS81C1202
19.4 External Interrupt
The external interrupt on INT0 and INT1 pins are edge
triggered depending on the edge selection register IEDS
(address 0E6H) as shown in Figure 19-6 .
ADDRESS : 0E6H
RESET VALUE : 00000000
Ext. Interrupt Edge Selection
The edge detection of external interrupt has three transition
activated mode: rising edge, falling edge, and both edge
Register
W
W
W
W
W
W
W
W
IEDS
.
INT1 edge select
INT0 edge select
INT0 pin
INT1 pin
INT0IF
INT1IF
00: Int. disable
01: falling
10: rising
00: Int. disable
01: falling
10: rising
INT0 INTERRUPT
INT1 INTERRUPT
11: both
11: both
IEDS
[0E6H]
Response Time
Figure 19-6 External Interrupt Block Diagram
The INT0 and INT1 edge are latched into INT0IF and
INT1IF at every machine cycle. The values are not actually
polled by the circuitry until the next machine cycle. If a re-
quest is active and conditions are right for it to be acknowl-
edged, a hardware subroutine call to the requested service
routine will be the next instruction to be executed. The
DIV itself takes twelve cycles. Thus, a minimum of twelve
complete machine cycles elapse between activation of an
external interrupt request and the beginning of execution
of the first instruction of the service routine.
Example: To use as an INT0 and INT1
:
:
;**** Set port as an input port RB2,RB3
LDM
;
RBIO,#1111_0011B
;
;**** Set port as an interrupt port
LDM
;
;
RBFUNC,#0C0H
;**** Set Falling-edge Detection
LDM
:
:
IEDS,#0000_0101B
Below shows interrupt response timings.
max. 12 fOSC
8 fOSC
Interrupt
goes
active
Interrupt
latched
Interrupt
processing
Interrupt
routine
Figure 19-7 Interrupt Response Timing Diagram
Jan. 2002 ver 2.0
61
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