GMS81C1102 / GMS81C1202
The operation within data memory (RAM)
ASL, BIT, DEC, INC, LSR, ROL, ROR
X indexed direct page, auto increment→ {X}+
In this mode, a address is specified within direct page by
the X register and the content of X is increased by 1.
Example; Addressing accesses the address 0035H .
983500 INC
!0035H
;A ←RAM[035H]
LDA, STA
Example; X=35H
DB
LDA
{X}+
0035H
data
➌
➋
~
~
~
~
data+1 → data
35H
data
➋
0FA00H
0FA01H
0FA02H
98
35
00
➊
data → A
36H → X
~
~
~
~
address: 0035
➊
DB
(5) Indexed Addressing
X indexed direct page (no offset) → {X}
In this mode, a address is specified by the X register.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA
Example; X=15H
X indexed direct page (8 bit offset) → dp+X
This address value is the second byte (Operand) of com-
mand plus the data of ꢀ-register. And it assigns the mem-
ory in Direct page.
ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA
STY, XMA, ASL, DEC, INC, LSR, ROL, ROR
D4
LDA
{X}
;ACC←RAM[X].
Example; X=015H
C645
LDA
45H+X
15H
data
➋
data → A
~
~
~
~
➊
5AH
data
D4
0FA50H
➌
data → A
~
~
~
➋
~
0FB50H
0FB51H
C6
45
➊
45H+15H=5AH
Jan. 2002 ver 2.0
35
HYNIX [ HYNIX SEMICONDUCTOR ]
