GMS81C1102 / GMS81C1202
12.3 Data Memory
Figure 12-6 shows the internal Data Memory space avail-
able. Data Memory is divided into two groups, a user
RAM(including Stack) and control registers.
Address
Symbol
R/W
RESET Value
C0H
C1H
C2H
C3H
C4H
C5H
CAH
CBH
CCH
D0H
D1H
D1H
D1H
D2H
D3H
D3H
D4H
D4H
D4H
D5H
DEH
E2H
E3H
E4H
E5H
E6H
EAH
EBH
ECH
ECH
EDH
EFH
RA
RAIO
RB
RBIO
RC
RCIO
RAFUNC
RBFUNC
PUPSEL
TM0
R/W
W
R/W
W
R/W
W
W
W
W
R/W
R
W
R
R/W
W
W
R
R
R/W
W
Undefined
0000_0000
Undefined
---0_0000
Undefined
----_--00
0000_0000
---0_0000
----_--00
--00_0000
0000_0000
1111_1111
0000_0000
0000_0000
1111_1111
1111_1111
0000_0000
0000_0000
0000_0000
----_0000
1111_1111
0000_----
000-_----
0000_----
000-_----
----_0000
--00_0001
Undefined
0000_0000
-001_0111
0111_1111
----_-100
00H
DATA
MEMORY
(including STACK)
7FH
C0H
T0
TDR0
CDR0
TM1
TDR1
T1PPR
T1
CDR1
T1PDR
PWMHR
BUR
IENH
IENL
IRQH
IRQL
IEDS
ADCM
ADCR
BITR
CKCTLR
WDTR
PFDR
CONTROL
REGISTERS
FFH
Figure 12-6 Data Memory Map
Internal Data Memory addresses are always one byte wide,
which implies an address space of 128 bytes including the
stack area.
W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
W
R/W
R/W
The stack pointer should be initialized within 00H to 7FH
by software because its value is undefined after RESET.
The Stack area is defined at the Data Memory area, so the
stack should not be overlapped by manipulating RAM Da-
ta. For example, we assumed the Stack pointer is 6F. If this
address is accessed by program, the stack value is changed.
So the malfunction is occurred.
The control registers are used by CPU and Peripheral func-
tions for controlling the desired operation of the device.
Therefore these registers contain control and status bits for
the interrupt system, the timer/ counters, analog to digital
converters, I/O ports. The control registers are in address
C0H to FFH.
Table 12-3 RESET Value of Control Registers
Note: Several names are given at same address. Refer to
below table.
Note that unoccupied addresses may not be implemented
on the chip. Read accesses to these addresses will in gen-
eral return random data, and write accesses will have an in-
determinate effect.
When read
When write
Addr.
Timer
Mode
Capture
Mode
PWM
Mode
Timer
PWM
Mode
Mode
TDR0
TDR1
-
More detail informations of each register are explained in
each peripheral sections.
D1H
D3H
D4H
ECH
T0
CDR0
-
-
-
T1PPR
T1PDR
Note: Write only registers can not be accessed by bit ma-
nipulation instruction. Do not use read-modify-write
instruction. Use byte manipulation instruction.
T1
CDR1 T1PDR
BITR
CKCTLR
Table 12-4 Various Register Name in Same Adress
Example; To write at CKCTLR
LDM
CKCTLR,#09H;Divide ratio ÷16
Jan. 2002 ver 2.0
31
HYNIX [ HYNIX SEMICONDUCTOR ]
