GMS81C1102 / GMS81C1202
Address
C0H
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RA
RA Port Data Register
RA Port Direction Register
RB Port Data Register
RB Port Direction Register
RC Port Data Register
RC Port Direction Register
C1H
RAIO
C2H
RB
C3H
RBIO
C4H
RC
C5H
RCIO
RAFUNC
RBFUNC
PUPSEL
TM0
CAH
CBH
CCH
D0H
ANSEL7
ANSEL6
ANSEL5
ANSEL4
PWMO
-
ANSEL3
INT1I
-
ANSEL2
INT0I
-
ANSEL1
BUZO
ANSEL0
AVREFS
-
-
-
-
-
-
-
-
PUPSEL1 PUPSEL0
CAP0
T0CK2
T0CK1
T0CK0
T0CN
T0ST
T0/TDR0/
CDR0
D1H
D2H
D3H
Timer0 Register / Timer Data Register 0 / Capture Data Register 0
POL 16BIT PWME CAP1 T1CK1 T1CK0
Timer Data Register 1/ PWM Period Register 1
TM1
T1CN
T1ST
TDR1/
T1PPR
T1/CDR1/
T1PDR
D4H
Timer1 Register / Capture Data Register 1 / PWM Duty Register 1
PWM High Register
D5H
DEH
E2H
E3H
E4H
E5H
E6H
EAH
EBH
ECH
PWMHR
BUR
BUCK1
INT0E
ADE
INT0IF
ADIF
-
BUCK0
INT1E
WDTE
INT1IF
WDTIF
-
BUR5
T0E
BUR4
BUR3
BUR2
BUR1
BUR0
IENH
IENL
T1E
-
-
-
-
BITE
T0IF
BITIF
-
-
-
-
-
-
IRQH
IRQL
T1IF
-
-
-
-
-
-
-
-
-
-
IEDS
IED1H
ADS1
IED1L
ADS0
IED0H
ADST
IED0L
ADSF
ADCM
ADCR
-
-
ADEN
ADS2
ADC Result Data Register
Basic Interval Timer Data Register
BITR1
CKCTLR
Note1
ECH
-
WAKEUP RCWDT
WDTON
BTCL
-
BTS2
BTS1
BTS0
PFDS
EDH
EFH
WDTR
PFDR2
WDTCL 7-bit Watchdog Counter Register
-
-
-
-
PFDIS
PFDM
Table 12-5 Control Registers of GMS81C1202
These registers of shaded area can not be accessed by bit manipulation instruction as “SET1, CLR1”, so should be accessed by
register operation instruction as “LDM dp,#imm”.
1.
2.
The register BITR and CKCTLR are located at same address. Address ECH is read as BITR, written to CKCTLR.
The register PFDR only be implemented on devices, not on In-circuit Emulator.
Jan. 2002 ver 2.0
33
HYNIX [ HYNIX SEMICONDUCTOR ]
