Chapter 4. Peripheral Hardware
Timer2 mode Register
7
0
-
-
-
T2ST
T2CN
T2SL2
T2SL1
T2SL0
TM2
R/W <00D2H>
T2SL2
T2SL1
T2SL0
Input Clock Sel.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PS5
PS6
PS7
PS8
PS9
PS10
PS11
(
(
(
(
(
(
(
8us)
16us)
32us)
64us)
128us)
256us)
512us)
PS12 (1,024us)
T2cn
Timer2 Counter Continuation / Pause Control
0
1
Count Pause
Count Continuation
T2ST
Timer2 Start / Stop Control
0
1
Timer2 Stop
Timer2 Start after Clear
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