Chapter 4. Peripheral Hardware
4.2.3 Timer0, Timer1
TIMER0 and TIMER1 have an up-counter. When value of the up-counter
reaches the content of Timer Data Register(TDR), the up-counter is cleared to
¡ È
¡ È
00H , and interrupt(IFT0, IFT1) is occured at the next clock
Fig. 4. 10 Operatiion of Timer0
Concurrence
Concurrence
Concurrence
T0 Data
Registers
Value
T0 Value
0
CLEAR
CLEAR
CLEAR
INTERRUPT
INTERRUPT
INTERRUPT
IFT0
Interval period
For Timer0, the internal clock(PS) and the external clock(EC) can be selected as
counter clock. But Timer1 and Timer2 use only internal clock. As internal clock.
Timer0 can be used as internal-timer which period is determined by Timer Data
Register(TDR). Chosen as external clock, Timer0 executes as event-counter.
The counter execution of Timer0 and Timer1 is controlled by T0CN, T0ST,
CAP0, T1CN, T1ST, of Timer Mode Register TM0 and TM1. T0CN, T1CN are
used to stop and start Timer0 and Timer1 without clearing the counter. T0ST,
T1ST is used to clear the counter. For clearing and starting the counter, T0ST
¡ È ¡ È
¡ È ¡ È
and then set to 1 . T0CN,
or T1ST should be temporarily set to
0
¡ È ¡ È
T1CN, T0ST and T1ST should be set 1 , when Timer counting-up.
Controlling of CAP0 enables Timer0 as input capture. By programming of CAP0
¡ È ¡ È
to 1 , the period of signal from INT2 can be measured and then, event
counter value for INT2 can be read.
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HYNIX [ HYNIX SEMICONDUCTOR ]
