Chapter 4. Peripheral Hardware
Timer1 mode Register
7
0
T1ST
T1CN
T1MOD
T1IFS
-
T1SL2
T1SL1
T1SL0
TM1
R/W <00D1H>
T1SL2
T1SL1
T1SL0
Input Clock Sel.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PS0 (250ns)
PS1 (500ns)
PS2
PS3
(
(
1us)
2us)
PS7 ( 32us)
PS8 ( 64us)
PS9 (128us)
PS10 (256us)
T1IFS
Timer1 Interrupt Sel.
0
1
Interrupt Every Counter Overflow
Interrupt Every 2nd Counter Overflow
T1MOD
Timer1 Single / Modulo-N Sel.
0
1
Modulo-N
Single Mode
T1CN
Timer1 Countern Continuation / Pause Control
0
1
Count Pause
Count Continuation
T1ST
Timer1 Start/Stop control
0
1
Timer1 Stop
Timer1 Start after Clear
4 - 16
HYNIX [ HYNIX SEMICONDUCTOR ]
