Chapter 4. Peripheral Hardware
During counting-up, value of counter can be read. Timer execution is stopped by the
¡ È ¡ È
L )
reset signal (RESET =
(Note) in the process of reading 16-bit Timer Data, first read the upper 8-bit data. Then
read the lower 8-bit data, and read the upper 8-bit data again. If the earlier read upper
8-bit data are matched with the later read upper 8-bit data, read 16-bit data are correct.
If not, caution should be taken in the selection of upper 8-bit data.
Example)
1) Upper 8-bit Read 0A 0A
2) Lower 8-bit Read FF 01
3) Upper 8-bit Read 0B 0B
¡ é ¡ é
0AFF 0B01
4.2.3.1 Single/Modulo-N Mode
Timer0 (Timer1) can select initial (T0INIT, T1INIT of TM0, TM1) output level of Timer
¡ È ¡ È
, Low-Data Register value of Timer Data Register is
Output port. If initial level is
L
¡ È
¡ È
transferred to comparator and T0OUT(T1OUT) is to be Low , if initial level is
¡ È ¡ È ¡ È ¡ È
High , High -Data Register is transferred and to be High . Single Mode can be
¡ È ¡ È
set by Mode Select bit(T0MOD, T1MOD) of Timer Mode Register (TM0, TM1) to
1
When used as Single Mode, Timer counts up and compares with value of Data Register.
If the result is same, Time Out interrupt occurs and level of Timer Output port toggle,
then counter stops as reset state. When used as Modulo-N Mode, T0MOD(T1MOD)
¡ È ¡ È
. Counter counts up until the value of Data Register and occurs
should be set
0
Time-out interrupt. The level of Timer Output port toggle and repeats process of
counting the value which is selected in Data Register. During Modulo-N Mode, If
¡ È ¡ È
, Interrupt occurs on every
interrupt select bit(T0IFS, T1IFS) of Mode Register is
¡ È ¡ È
1 , Interrupt occurs every second time-out.
0
Time-out. If it is
(*note. Timer Output is toggled whenever time out happen)
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HYNIX [ HYNIX SEMICONDUCTOR ]
