Chapter 4. Peripheral Hardware
Timer0 mode Register
7
0
CAP0
T0ST
T0CN
T0MOD
T0IFS
T0SL2
T0SL1
T0SL0
TM0
R/W <00D0H>
T0SL2
T0SL1
T0SL0
Input Clock Sel.
Notes
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PS0 (250ns)
PS1 (500ns)
*
PS2
PS3
PS4
PS5
(
(
(
(
1us)
2us)
4us)
8us)
PS11 (512us)
EC
Event
Counter
T0IFS
Timer0 Interrupt Sel.
0
1
Interrupt Every Counter Overflow
Interrupt Every 2nd Counter Overflow
T0MOD
Timer0 Single / Modulo-N Sel.
0
1
Modulo-N
Single Mode
T0CN
Timer0 Counter Continuation / Pause Control
0
1
Count Pause
Count Continuation
T0ST
Timer0 Start/Stop control
0
1
Timer0 Stop
Timer0 Start after Clear
CAP0
Timer0 Interrupt Sel.
0
1
Timer/Counter
Input Capture*
*PS1 : not supporting input capture.
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HYNIX [ HYNIX SEMICONDUCTOR ]
