impedance state after a few
cycles of the Isolated Modulator’s
clock.
sion cycle. A logic low level
Digital Interface
Timing
selects channel one, a high level
selects channel 2. CHAN should
not be changed during a conver-
sion cycle. The state of the CHAN
signal has no effect on the
behavior of either the over-range
detection circuit (OVR1) or the
adjustable threshold detection
circuit (THR1). Both OVR1 and
THR1 continuously monitor
channel 1 independent of the
CHAN signal. CHAN also does not
affect the behavior of the pre-
trigger circuit, which is tied to
the conversion timing of channel
1, as explained in the Digital
Interface Configuration section.
Power Up/Reset
At power up, the digital interface
IC should be reset either
manually, by bringing the RESET
pin (pin 9) high for at least
100 ns, or automatically by
connecting a 10 µF capacitor
The amount of time between the
falling edge of CS and the rising
edge of SDAT depends on which
conversion and pre-trigger modes
are selected; it can be as low as
0.7 µs when using pre-trigger
mode 2, as explained in the
Digital Interface Configuration
section.
between the RESET pin and V
DD
(pin 16). The RESET pin operates
asynchronously and places the IC
in its default configuration, as
specified in the Digital Interface
Configuration section.
Serial Configuration
Timing
The HCPL-x870 Digital Interface
IC is programmed using the
Serial Configuration Interface
(SCI) which consists of the clock
(CCLK), data (CDAT), and
Conversion Timing
Figure 19 illustrates the timing
for one complete conversion
cycle. A conversion cycle is
Digital Interface
Configuration
Configuration Registers
The Digital Interface IC contains
four 6-bit configuration registers
that control its behavior. The two
LSBs of any byte clocked into the
serial configuration port (CDAT,
CCLK, CLAT) are used as address
bits to determine which register
the data will be loaded into.
initiated on the falling edge of the
convert start signal (CS); CS
should be held low during the
entire conversion cycle. When CS
is brought low, the serial output
data line (SDAT) changes from a
high-impedance to the low state,
indicating that the converter is
busy. A rising edge on SDAT
indicates that data is ready to be
clocked out. The output data is
clocked out on the negative edges
of the serial clock pulses (SCLK),
MSB first. A total of 16 pulses is
needed to clock out all of the data.
After the last clock pulse, CS
should be brought high again,
causing SDAT to return to a high-
impedance state, completing the
conversion cycle. If the external
circuit uses the positive edges of
SCLK to clock in the data, then a
total of sixteen bits is clocked in,
the first bit is always high
enable/latch (CLAT) signals.
Figure 18 illustrates the timing
for the serial configuration inter-
face. To send a byte of configura-
tion data to the HCPL-x870, first
bring CLAT low. Then clock in
the eight bits of the configuration
byte (MSB first) using CDAT and
the rising edge of CCLK. After the
last bit has been clocked in,
bringing CLAT high again will
latch the data into the appropri-
ate configuration register inside
the interface IC. If more than
eight bits are clocked in before
CLAT is brought high, only the
last eight bits will be used. Refer
to the Digital Interface Configura-
tion section to determine appro-
priate configuration data. If the
default configuration of the
Registers 0 and 1 (with address
bits 00 and 01) specify the
conversion and offset calibration
modes of channels 1 and 2,
register 2 (address bits 10)
specifies the behavior of the
adjustable threshold circuit, and
register 3 (address bits 11)
specifies which pre-trigger mode
to use for channel 1. These
registers are illustrated in Table 3
below, with default values
digital interface IC is acceptable,
then CCLK, CDIN and CLAT may
indicated in bold italic type. Note
that there are several reserved
bits which should always be set
low and that the configuration
registers should not be changed
during a conversion cycle.
be connected to either V or
DD
(indicating that data is ready)
followed by 15 data bits. If fewer
than 16 cycles of SCLK are input
before CS is brought high, the
conversion cycle will terminate
and SDAT will go to the high-
GND.
Channel Select Timing
The channel select signal (CHAN)
determines which input channel
will be used for the next conver-
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HP [ HEWLETT-PACKARD ]
