Table 3. Register Configuration.
Configuration Data Bits
Address Bits
Register
Bit 7
High
High
Bit 6
Bit 5
Bit 4
Low
Low
Bit 3
Channel 1
Offset Cal
Bit 2
Reserved
Bit 1
Low
Low
Bit 0
Channel 1 Conversion Mode
0
High
Low
Low
Channel 2
Offset Cal
Low
Reserved
Low
Channel 2 Conversion Mode
1
High
Threshold
Detection Time
Low
Low
Low
High
Threshold Level
2
3
High
Pre-Trigger Mode
Low
Low
Low
Low
Low
Low
Low
Low
High
High
Low
Reserved
Low
Low
Low
High
Note: Bold italic type indicates default values. Reserved bits should be set low.
Conversion Mode
a summary of how performance
changes as a function of conver-
sion mode setting. Combinations
of data bits not specified in Table
4 below are not recommended.
determine the conversion mode
for the appropriate channel. The
bit settings for choosing a partic-
ular conversion mode are shown
in Table 4 below. See Table 2 for
The conversion mode determines
the speed/resolution trade-off for
the Isolated A/D converter. The
four MSBs of registers 0 and 1
Table 4. Conversion Mode Configuration.
Configuration Data Bits
Conversion
Mode
Bit 7
Low
Low
High
High
High
Bit 6
High
Low
Bit 5
Low
High
High
Low
High
Bit 4
High
High
Low
Low
Low
1
2
3
4
5
High
High
Low
Note: Bold italic type indicates default values.
1-280
HP [ HEWLETT-PACKARD ]
