HI-8050/51, HI-8150/51
LD
CL
CS
DIN
1M W
1mF
1M W
BPOUT
CS CL LD
DIN DO
CS CL LD
CS CL LD
1mF
DIN
DO
DIN
DO
R
C
BPIN BPOUT
BPOSC
BPIN BPOUT
BPOSC
BPIN BPOUT
BPOSC
1M W
1mF
1M W
360p
1mF
BACK
PLANE
SEGMENTS
SEGMENTS
SEGMENTS
Figure 4. OFFSET MEASUREMENT
Figure 3. RC OSCILLATOR AND CASCADED
DEVICES
DATA IN
DATA IN
DIN ⇒
DIN ⇒
DOUT
⇒
38 Stage
38 Stage
DOUT
⇒
Shift Register
Shift Register
CL ⇒
CS ⇒
CL ⇒
CS ⇒
CLK
CLK
Figure 5. HI-8010/HI-8110 CL & CS LOGIC
(8020OPT = OPEN or HIGH)
Figure 6. HI-8020/HI-8120 CL & CS LOGIC
(8020OPT = LOW)
CL
INPUT
tCL
tCW
DIN
INPUT
tDS
tDH
CS
INPUT
tCSS
tLCS
tCSL
tCSH
LD
INPUT
tLW
tLS
tCDO
DOUT
VALID
OUTPUT (8020OPT float or high)
tCDO
DOUT
OUTPUT (8020OPT low)
VALID
VALID
Figure 7. TIMING DIAGRAM
HOLT INTEGRATED CIRCUITS
4
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
