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HI-3282PQM 参数 Datasheet PDF下载

HI-3282PQM图片预览
型号: HI-3282PQM
PDF下载: 下载PDF文件 查看货源
内容描述: ARINC 429串行发送器和双接收机 [ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER]
分类和应用: 微控制器和处理器串行IO控制器通信控制器外围集成电路接收机数据传输时钟
文件页数/大小: 13 页 / 146 K
品牌: HOLTIC [ HOLT INTEGRATED CIRCUITS ]
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HI-3282  
will also be placed into the transmitter FIFO. SEL is then taken high  
FUNCTIONAL DESCRIPTION (cont.)  
and EN is strobed again to place the upper byte of the data word on  
the data bus. By strobing PL2 at the same time as EN, the second  
byte will also be placed into the FIFO. The data word is now ready to  
be transmitted according to the parity programmed into the control  
word register.  
REPEATER OPERATION  
The repeater mode of operation allows a data word that has been  
received by the HI-3282 to be placed directly into its FIFO for  
transmission. After a 32-bit word has been shifted into the receiver  
shift register, the D/R flag will go low. Alogic "0" is placed on the SEL  
line and EN is strobed. This is the same procedure as for normal  
receiver operation and it places the lower byte (16) of the data word  
on the data bus. By strobing PL1 at the same time as EN, the byte  
In normal operation, either byte of a received data word may be read  
from the receiver latches first by use of SEL input. During repeater  
operation however, the lower byte of the data word must be read  
first. This is necessary because, as the data is being read, it is also  
being loaded into the FIFO and the transmitter FIFO is always  
loaded with the lower byte of the data word first.  
TIMING DIAGRAMS  
DATA RATE - EXAMPLE PATTERN  
429DO  
429DO  
ARINC BIT  
DATA  
NULL  
DATA  
DATA  
NULL  
NULL  
BIT 1  
NEXT WORD  
WORD GAP  
BIT 32  
BIT 31  
BIT 30  
LOADING CONTROL WORD  
VALID  
DATA BUS  
tCWSET  
tCWHLD  
CWSTR  
tCWSTR  
RECEIVER OPERATON  
BIT 31  
BIT 32  
ARINC DATA  
DATA READY FLAG D/R  
tEND/R  
tEN  
tD/R  
DON'T CARE  
DON'T CARE  
DON'T CARE  
BYTE SELECT SEL  
tSELEN  
tSELEN  
tENSEL  
tENSEL  
ENABLE BYTE ON BUS EN  
tENEN  
tD/REN  
tDATAEN  
tDATAEN  
BYTE 1 VALID  
BYTE 2 VALID  
DATA BUS  
tENDATA  
tENDATA  
HOLT INTEGRATED CIRCUITS  
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