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HI-3282PQM 参数 Datasheet PDF下载

HI-3282PQM图片预览
型号: HI-3282PQM
PDF下载: 下载PDF文件 查看货源
内容描述: ARINC 429串行发送器和双接收机 [ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER]
分类和应用: 微控制器和处理器串行IO控制器通信控制器外围集成电路接收机数据传输时钟
文件页数/大小: 13 页 / 146 K
品牌: HOLTIC [ HOLT INTEGRATED CIRCUITS ]
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HI-3282  
FUNCTIONAL DESCRIPTION (cont.)  
The parity generator counts the ONES in the 31-bit word. If the BD12  
control word bit is set low, the 32nd bit transmitted will make parity  
odd. If the control bit is high, the parity is even.  
TRANSMITTER  
Ablock diagram of the transmitter section is shown in Figure 3.  
FIFO OPERATION  
SELF TEST  
If the BD05 control word bit is set low, 429DO or 429DO are internally  
connected to the receivers inputs, bypassing the interface circuitry.  
Data to Receiver 1 is as transmitted and data to Recevier 2 is the  
complement. 429DO and 429DO outputs remain active during self  
test.  
The FIFO is loaded sequentially by first pulsing PL1 to load byte 1  
and then PL2 to load byte 2. The control logic automatically loads  
the 31 bit word in the next available position of the FIFO. If TX/R,  
the transmitter ready flag, is high (FIFO empty), then 8 words,  
each 31 bits long, may be loaded. If TX/R is low, then only the  
available positions may be loaded. If all 8 positions are full, the  
FIFO ignores further attempts to load data.  
SYSTEM OPERATION  
The two receivers are independent of the transmitter. Therefore,  
control of data exchanges is strictly at the option of the user. The only  
restrictions are:  
DATATRANSMISSION  
When ENTX goes high, enabling transmission, the FIFO  
positions are incremented with the top register loading into the  
data transmission shift register. Within 2.5 data clocks the first  
data bit appears at either 429DO or 429DO. The 31 bits in the  
data transmission shift register are presented sequentially to the  
outputs in theARINC 429 format with the following timing:  
1. The received data may be overwritten if not retrieved within  
oneARINC word cycle.  
2. The FIFO can store 8 words maximum and ignores attempts  
to load addition data if full.  
HIGH SPEED LOW SPEED  
3. Byte 1 of the transmitter data must be loaded first.  
ARINC DATABITTIME  
DATABITTIME  
NULLBITTIME  
10 Clocks  
5 Clocks  
5 Clocks  
40 Clocks  
80 Clocks  
40 Clocks  
40 Clocks  
320 Clocks  
4. Either byte of the received data may be retrieved first. Both  
bytes must be retrieved to clear the data ready flag.  
WORD GAPTIME  
5. After ENTX, transmission enable, goes high it cannot go low  
until TX/R, transmitter ready flag, goes high. Otherwise, one  
ARINC word is lost during transmission.  
The word counter detects when all loaded positions are  
transmitted and sets the transmitter ready flag, TX/R, high.  
MASTER RESET (MR)  
TRANSMITTER PARITY  
On a Master Reset data transmission and reception are immedi-  
ately terminated, the transmit FIFO and receivers cleared as are  
the transmit and receive flags. The Control Register is not affected  
by a Master Reset.  
Control register bit BD04 (PAREN) enables parity bit insertion into  
transmitter data bit 32. Parity is always inserted if DBCEN is open  
or high. If DBCEN is low, logic 0 on PAREN inserts data on bit 32,  
and logic 1 on PAREN inserts parity on bit 32.  
DBCEN  
PARITY  
GENERATOR  
CONTROL REGISTER BD04, BD12  
DATA AND  
NULL TIMER  
SEQUENCER  
429DO  
429DO  
BIT CLOCK  
31 BIT PARALLEL  
LOAD SHIFT REGISTER  
BIT  
AND  
WORD GAP  
COUNTER  
WORD CLOCK  
START  
SEQUENCE  
TX/R  
WORD COUNTER  
AND  
FIFO CONTROL  
ADDRESS  
ENTX  
8 X 31 FIFO  
INCREMENT  
WORD COUNT  
FIFO  
LOADING  
SEQUENCER  
LOAD  
PL1  
PL2  
DATA  
CLOCK  
CLK  
DATA CLOCK  
DIVIDER  
TX CLK  
DATA BUS  
CONTROL REGISTER  
BIT BD13  
FIGURE 3. TRANSMITTER BLOCK DIAGRAM  
HOLT INTEGRATED CIRCUITS  
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