HI-3282
ARINC 429 DATA FORMAT
FUNCTIONAL DESCRIPTION
The following table shows the bit positions in exchanging data with
the receiver or the transmitter. ARINC bit 1 is the first bit
transmitted or received.
CONTROL WORD REGISTER
The HI-3282 contains 11 data flip flops whose D inputs are con-
nected to the data bus and clocks connected to CWSTR. Each
flip flop provides options to the user as follows:
BYTE 1
DATA
BUS
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
DATA
BUS
PIN
FUNCTION CONTROL
DESCRIPTION
ARINC
BIT
13 12 11 10
9
31 30 32
1
2
3
4
5
6
7
8
BD04
BDO5
BDO6
BDO7
BDO8
BDO9
BD10
BD11
PAREN
Enables parity bit insertion into
Transmitter data bit 32
BYTE 2
If enabled, an internal connection
is made passing 429DO and
429DO to the receiver logic inputs
DATA
BUS
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
SELF TEST 0 = ENABLE
RECEIVER 1
ARINC
BIT
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
If enabled, ARINC bits 9 and,
10 must match the next two
control word bits
DECODER
1 = ENABLE
If Receiver 1 Decoder is
enabled, the ARINC bit 9
must match this bit
THE RECEIVERS
-
-
-
ARINC BUS INTERFACE
If Receiver 1 Decoder is
enabled, the ARINC bit 10
must match this bit
-
Figure 1 shows the input circuit for each receiver. The ARINC 429
specification requires the following detection levels:
RECEIVER 2
DECODER
If enabled, ARINC bits 9 and
10 must match the next two
control word bits
1 = ENABLE
STATE
DIFFERENTIALVOLTAGE
ONE
NULL
ZERO
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
If Receiver 2 Decoder is
enabled, then ARINC bit 9
must match this bit
-
-
-
-
If Receiver 2 Decoder is
enabled, then ARINC bit 10
must match this bit
The HI-3282 guarantees recognition of these levels with a common
mode Voltage with respect to GND less than 5V for the worst case
condition (4.75V supply and 13V signal level).
INVERT
XMTR
PARITY
Logic 0 enables normal odd parity
1 = ENABLE and Logic 1 enables even parity
output in transmitter 32nd bit
BD12
BD13
BD14
The tolerances in the design guarantee detection of the above
levels, so the actual acceptance ranges are slightly larger. If the
ARINC signal is out of the actual acceptance ranges, including the
nulls, the chip rejects the data.
XMTR DATA
CLK SELECT
0 = ÷10
1 = ÷80
CLK is divided either by 10 or
80 to obtain XMTR data clock
RCVR DTA
CLK SELECT
0 = ÷10
1 = ÷80
CLK is divided either by 10 or
80 to obtain RCVR data clock
DIFFERENTIAL
COMPARATORS
AMPLIFIERS
v
cc
429DI1 (A)
OR
ONES
429DI2 (A)
NULL
GND
v
cc
ZEROES
429DI1 (B)
OR
429DI2 (B)
GND
FIGURE 1. ARINC RECEIVER INPUT
HOLT INTEGRATED CIRCUITS
3
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
