HI-3282
FUNCTIONAL DESCRIPTION (cont.)
RECEIVER LOGIC OPERATION
EN1 retrieves data from receiver 1 and EN2 retrieves data from
receiver 2.
Figure 2 shows a block diagram of the logic section of each
receiver.
If another ARINC word is received and a new EOS occurs before
the two bytes are retrieved, the data is overwritten by the new
word.
BIT TIMING
The ARINC 429 specification contains the following timing
specification for the received data:
INTERNAL LIGHTNING PROTECTION (-10 Only)
The HI-3282-10 configurations are similar to the HI-3282 except
that the ARINC inputs are internally lightning protected to
DO-160D, Level 3 through 10 Kohm resistors that must be
connected in series with each input from the ARINC bus.
HIGH SPEED
LOW SPEED
BIT RATE
100K BPS 1ꢀ 12K -14.5K BPS
PULSE RISE TIME 1.5 0.5 µsec
PULSE FALL TIME 1.5 0.5 µsec
10 5 µsec
10 5 µsec
5 µsec 5ꢀ 34.5 to 41.7 µsec
PULSE WIDTH
The design of the HI-3282-10 device requires the external
10 Kohm series resistors for proper ARINC level detection. The
typical 10 volt differential signal is translated and input to a
window comparator and latch. The comparator levels are set so
that, with the external 10 Kohm resistors, they are just below the
standard 6.5 V minimum ARINC data threshold and just above the
2.5 V maximum ARINC null threshold.
RECEIVER PARITY
The receiver parity circuit counts Ones received, including the
parity bit, ARINC bit 32. If the result is odd, then "0" will appear in
the 32nd bit.
RETRIEVING DATA
The receivers of the HI-3282-10 when used with external 10
Kohm resistors will withstand DO-160D, Level 3, waveforms 3, 4
and 5A. No additional lightning protection circuit is necessary.
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). If the receiver decoder is enabled and
the 9th and 10th ARINC bits match the control word program bits
or if the receiver decoder is disabled, then EOS clocks the data
ready flag flip flop to a "1", D/R1 or D/R2 (or both) will go low. The
data flag for a receiver will remain low until after both ARINC bytes
from that receiver are retrieved. This is accomplished by
activating EN with SEL, the byte selector, low to retrieve the first
byte and activating EN with SEL high to retrieve the second byte.
APPLICATION NOTE 300
Please refer to the Holt AN-300 Application Note for additional
information and recommendations on lightning protection of Holt
Line Drivers and Receivers.
TO PINS
SEL
MUX
32 TO 16 DRIVER
CONTROL
CLOCK
OPTION
CONTROL
BIT BD14
CLK
EN
D/R
CLOCK
LATCH
ENABLE
CONTROL
DECODER
CONTROL
BITS
32 BIT LATCH
/
BIT
COUNTER
AND
END OF
SEQUENCE
BITS 9 & 10
32ND
BIT
DATA
PARITY
CHECK
32 BIT SHIFT REGISTER
BIT CLOCK
EOS
EOS
WORD GAP
TIMER
WORD GAP
ONES
NULL
SHIFT REGISTER
BIT CLOCK
END
START
SEQUENCE
CONTROL
SHIFT REGISTER
SHIFT REGISTER
ERROR
CLOCK
ZEROS
ERROR
DETECTION
FIGURE 2. RECEIVER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
4
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
