HI-3200, HI-3201
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SPI Mode 0
MSB
LSB
SI
Command Byte
MSB
LSB MSB
High Z
High Z
SO
CS
Data Byte
Host may continue to assert CS
here to read sequential byte(s)
when allowed by the instruction.
Each byte needs 8 SCK clocks.
FIGURE 2. Single-Byte Read From RAM or a Register
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SPI Mode 0
MSB
LSB MSB
LSB MSB
LSB
SI
Command Byte
Data Byte 0
Data Byte 1
High Z
SO
CS
Host may continue to assert CS
here to write sequential byte(s)
when allowed by the SPI instruction.
Each byte needs 8 SCK clocks.
FIGURE 3. 2-Byte Write To RAM or a Register Pair
HOLT INTEGRATED CIRCUITS
47
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
