HI-3200, HI-3201
CAN Bus Received Data Status Byte Definition
NEWTX0
X
X
6
CAN RECEIVED DATA BLOCK STATUS BYTE
7
5
4
3
2
1
0
LSB
MSB
Bit Name
R/W Default Description
7
6
5
-
R/W
R/W
R/W
0
0
0
Not used
Not used
-
NEWHOST
This bit is set when a new CAN frame is received and stored in this block. It is reset when
the host CPU executes SPI instruction 0x9C to read the block.
4
3
2
1
0
NEWCAN
NEWTX3
NEWTX2
NEWTX1
NEWTX0
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
This bit is set when a new CAN frame is received and stored in this block. It is reset when
the CANTransmit scheduler reads any bytes from the block.
This bit is set when a new CAN frame is received and stored in this block. It is reset when
theARINC 429Transmit scheduler #3 reads any bytes from the block.
This bit is set when a new CAN frame is received and stored in this block. It is reset when
theARINC 429Transmit scheduler #2 reads any bytes from the block.
This bit is set when a new CAN frame is received and stored in this block. It is reset when
theARINC 429Transmit scheduler #1 reads any bytes from the block.
This bit is set when a new CAN frame is received and stored in this block. It is reset when
theARINC 429Transmit scheduler #0 reads any bytes from the block.
HOLT INTEGRATED CIRCUITS
25
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
