HI-3200, HI-3201
ARINC 429 Bit Monitor Pins
The HI-3200 has the capability of externally monitoring any
ARINC 429 received payload bit through the pins
ARXBIT[7:0] (Note: The HI-3200 provides external
monitoring of two bits through pinsARXBIT1 andARXBIT0,
whereas the HI-3201 provides external monitoring of eight
bits through pins ARXBIT7 to ARXBIT0). When the
appropriate ARINC 429 receiver is enabled and the target
label is received, the monitored bit value will be reflected on
the pin. This allows the user to monitor any ARINC 429
received payload bit without performing any host SPI reads.
The following registers configure the functionality of these
monitor pins. Note that all these control register bits are
RESETto zero.
ARXBIT0
PINS ARXBIT[7:0] REGISTER
(Address 0x805F)
7
6
5
4
3
2
1
0
LSB
MSB
Bit Name
R/W Default Description
R/W
7:0 ARXBIT[7:0]
0
These bits reflect the value of the corresponding pins ARXBIT[7:0]. After reset, all values are
zero. When a monitoredARINC 429 bit changes, this register is updated with the value, which
is reflected on the corresponding pin. The purpose of this register is to allow the user to preset
ARXBITvalues after chip reset.
the
ARXCR17
ARXCR10
PIN ARXBIT0 CONFIGURATION REGISTER 1
(Address 0x8060)
7
6
5
4
3
2
1
0
LSB
MSB
Bit Name
R/W Default Description
7:5 ARXCR1[7:5] R/W
0
These bits select which receive channel (0 through 7) will have bits monitored and reflected on
the pinARXBIT0.
4:0 ARXCR1[4:0] R/W
0
These bits select which bit (8 through 31) of the ARINC payload will be reflected on the pin
ARXBIT0. The receiver is specified by bits ARX0CR1[7:5] and the target label is specified
by pin ARXBIT0 Configuration Register 2 described below. Note that bits 0 through 7 of the
ARINC payload are not monitored and selecting these bits results in no effect.
ARXCR27
ARXCR20
PIN ARXBIT0 CONFIGURATION REGISTER 2
(Address 0x8061)
7
6
5
4
3
2
1
0
LSB
MSB
Bit Name
R/W Default Description
7:0 ARXCR2[7:0] R/W
0
These bits select which label (0 through 255) will have bits monitored and reflected on
the pin ARXBIT0. The receive channel and specific bits monitored are specified in ARXBIT0
Configuration Register 1 described above.
PINS ARXBIT1 Through ARXBIT7 CONFIGURATION REGISTERS
(Addresses 0x8062 to 0x806F)
Each pin ARXBIT1 through ARXBIT7 are also specified by a pair of configuration registers similar to ARXBIT0 described above.
Functionality is exactly the same. The register addresses for each pin specification are listed in the Register Map section (see page
11). Note that HI-3200 provides external monitoring of two bits through pins ARXBIT1 and ARXBIT0, whereas the HI-3201 provides
external monitoring of eight bits through pinsARXBIT7 toARXBIT0.
HOLT INTEGRATED CIRCUITS
22
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
