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HI-3111PCT 参数 Datasheet PDF下载

HI-3111PCT图片预览
型号: HI-3111PCT
PDF下载: 下载PDF文件 查看货源
内容描述: 航空电子与CAN收发器集成控制器 [Avionics CAN Controller with Integrated Transceiver]
分类和应用: 电子控制器航空
文件页数/大小: 53 页 / 178 K
品牌: HOLTIC [ HOLT INTEGRATED CIRCUITS ]
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HI-3110  
TRANSMIT ERROR COUNTER REGISTER: TEC  
TEC7:0  
(Write, SPI Op-code 0x26)  
(Read, SPI Op-code 0xEC)  
7
6
5
4
3
2
1
0
LSB  
MSB  
TheTEC register reflects the current value of the CANTransmit Error Counter. This register can be written by SPI command for test  
purposes.  
Bit Name  
R/W Default Description  
R/W 0x00 Transmit Error Counter bits <7:0>.  
7-0 TEC7:0  
0 £TEC £ 95: Error active status.  
96£TEC £ 127: Error active status. Error warning flag, ERRW, set in STATF register. This  
may be used to generate a hardware interrupt if ERRWIE bit is set in STATFE register.  
128 £TEC£ 255: Error passive status. Transmit error passive flag, TXERRP, set in ERR  
register. ERRPalso set in STATF register. This may be used to generate a hardware interrupt if  
ERRPIE bit is set in STATFE register.  
TEC > 255: Bus-off status. Bus-off flags, BUSOFF, set in ERR and STATF registers. The  
latter may be used to generate a hardware interrupt if BUSOFFIE bit is set in STATFE register.  
The HI-3110 will, after entering bus-off state, automatically recover to error active status  
without host intervention if the BOR bit is set in control register CTRL0 and 128 x 11  
consecutive recessive bits are detected on the bus. If the BOR bit is not set, bus-off recovery is  
managed by the host.  
RECEIVE ERROR COUNTER REGISTER: REC  
REC7:0  
(Write, SPI Op-code 0x24)  
(Read, SPI Op-code 0xEA)  
7
6
5
4
3
2
1
0
LSB  
MSB  
The REC register reflects the current value of the CAN Receive Error Counter. This register can be written by SPI command for test  
purposes.  
Bit Name  
R/W Default Description  
R/W 0x00 Receiver Error Counter bits <7:0>.  
7-0 TEC7:0  
0 £ REC £ 95: Error active status.  
96 £ REC £ 127: Error active status. Error warning flag, ERRW, set in STATF register. This  
may be used to generate a hardware interrupt if ERRWIE bit is set in STATFE register.  
128 £ REC £ 255: Error passive status. Receive error passive flag, RXERRP, set in ERR  
register. ERRPalso set in STATF register. This may be used to generate a hardware interrupt if  
ERRPIE bit is set in STATFE register.  
HOLT INTEGRATED CIRCUITS  
21  
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