HI-3110
BIT TIMING REGISTER 1: BTR1
TSEG
T
2
S
-2EG2-1
TSEGT1S-1EG1-0
(Write, SPI Op-code 0x1A)
(Read, SPI Op-code 0xD8)
7
6
5
4
3
2
1
0
LSB
MSB
BTR1 configures the CAN protocol bit timing segments in terms of time quanta (Tq) and sets the number of sampling points. This
register can be read anytime and written only in init mode (MODE<2:0> bits set to <1xx> in the CTRL0 register).
Bit Name
SAMP
R/W Default Description
7
R/W
0
Samples per bit.
This bit configures how many samples are taken per bit.
1
0
=
=
three samples per bit.
one sample per bit.
Notes:ARINC 825 states that there shall be only one sample per bit. Furthermore, it is
recommended to sample only once at higher CAN bit rates. Bit sampling occurs at the end of
Phase Seg1.
6-4 TSEG2-2:0
R/W
0
Time Segment 2 bits <2:0>.
Tseg2 = Phase Seg2 of the CAN protocol bit timing specification. BitsTSEG2-2:0 specify the
number of time quanta in Phase Seg2. Note: Not all combinations are valid, since Phase Seg
2 must be greater than SJW.
TSEG2 bits <2:0>
000: Not valid
001:Tseg2 = 2Tq clock cycles
010:Tseg2 = 3Tq clock cycles
.
etc.
.
111:Tseg2 = 8Tq clock cycles
3-0 TSEG1-3:0
R/W
0
Time Segment 1 bits <3:0>.
Tseg1 = Prop Seg + Phase Seg1 of the CAN protocol bit timing specification. BitsTSEG1-3:0
specify the number of time quanta in Prop Seg + Phase Seg1. Note: Not all combinations are
valid, since Prop Seg + Phase Seg1 ³Phase Seg 2. The CAN protocol states that the
minimum number of Tq in a bit time shall be 8.
TSEG1 bits <3:0>
0000: Not valid
0001:Tseg1 = 2Tq clock cycles
0010:Tseg1 = 3Tq clock cycles
0011:Tseg1 = 4Tq clock cycles
0100:Tseg1 = 5Tq clock cycles
.
.
.
1111: Tseg1 = 16Tq clock cycles
Notes: ARINC 825 states that the sample point shall not be less than 75% of the bit time. In
this case, Tseg1 should be a minimum of 5Tq for Phase Seg2 (Tseg2) = 2Tq and SJW = 1Tq.
HOLT INTEGRATED CIRCUITS
20
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
