HI-3110
ERROR REGISTER: ERR
TXER
R
R
X
P
ERRP
ACKESRTRUFERR
(Read only)
(Read, SPI Op-code 0xDC)
7
6
5
4
3
2
1
0
LSB
MSB
The ERR register indicates CAN bus status and protocol errors. It is read only. All bits default to 0 at power up and maintain their
current status following reset. Bits 4:0 are reset following a host read.
Bit Name
R/W Default Description
7
BUSOFF
R
0
Bus-off status indicator.
This bit is set whenTEC > 255. Node is in bus off condition. The bit is reset by HI-3110 when a
successful bus recovery sequence is detected (128 x 11 consecutive recessive bits). d the
FILHIT3:0 bits will reflect this value.
6
5
4
TXERRP
RXERRP
BITERR
R
R
R
0
0
0
Transmit Error Passive status indicator.
This bit is set when 128 £TEC £ 255.
Receive Error Passive status indicator.
This bit is set when 128 £ REC £ 255.
Bit Error.
Abit error was detected in a transmitted frame (the bit observed on the bus was opposite to
what was expected).
3
2
1
0
FRMERR
CRCERR
ACKERR
STUFERR
R
R
R
R
0
0
0
0
Form Error.
A Form error was detected in a receive frame.
CRC Error.
A CRC error was detected in a receive frame.
Acknowledgement Error.
AnACK error was detected in a receive frame.
Stuff Error.
Abit stuffing error was detected in a received frame.
HOLT INTEGRATED CIRCUITS
23
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
