HI-3110
BLOCK DIAGRAM
VLOGIC
BIT
TIMING
CS
REGISTERS
SCK
SPI BUS
SPI DECODE/
ENCODE
SI
VDD
GND
SO
TRANSMIT
LOGIC & FIFO
TXEN
GP2
HISTORY
FIFO
TRANSCEIVER
CANH
CANL
GP1
ERROR
STATUS
& CONTROL
INTERRUPTS
AND
STATUS
STAT
INT
RECEIVE
LOGIC & FIFO
SPLIT
(see ordering
information)
FILTERS
TIME-TAG
COUNTER
OSCIN
OSCILLATOR
OSCOUT
MR
CLOCK DIV
OUT
CLKOUT
(see ordering
information)
HI-3110
Figure 1. HI-3110 Block Diagram
PRIMARY FUNCTIONS OF HI-3110 LOGIC BLOCKS
SPI PROTOCOL BLOCK 8 message FIFO with optional filters
Handles data transfers between the host and the chip Forwards message data and optional time stamp to the host
REGISTERS BLOCK
Stores configuration data
ERROR BLOCK
Detects and records errors for protocol management
BIT TIMING BLOCK
Sets the data strobe and bit period
STATUS AND INTERRUPT
Provides hardware and software options for managing
communications
TRANSMIT BLOCK
Manages transmission protocol
8 message FIFO
Confirmation and time stamp of each message sent
is available in the History FIFO
OSCILLATOR
Configuration chooses either the crystal oscillator or and
external clock
TRANSCEIVER
Analog interface connects directly to the CAN bus
RECEIVER BLOCK
Manages reception protocol
HOLT INTEGRATED CIRCUITS
2
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
