HT48R063/064/065/066/0662/067
When an interrupt request is generated it takes 2 or 3 in-
struction cycle before the program jumps to the interrupt
vector. If the device is in the Sleep or Idle Mode and is
woken up by an interrupt request then it will take 3 cy-
cles before the program jumps to the interrupt vector.
HT48R066
Interrupt Source
Priority Vector
External Interrupt
1
2
3
4
04H
08H
0CH
10H
Timer/Event Counter 0 Overflow
Timer/Event Counter 1 Overflow
Time Base Overflow
Main
Program
Interrupt Request or
Interrupt Flag Set by Instruction
HT48R0662
Interrupt Source
N
Enable Bit Set ?
Priority Vector
External Interrupt
1
2
04H
08H
0CH
10H
14H
Y
Main
Automatically Disable Interrupt
Program
Timer/Event Counter 0 Overflow
Timer/Event Counter 1 Overflow
¾
Clear EMI & Request Flag
Wait for 2 ~ 3 Instruction Cycles
ISR Entry
3
¾
4
Time Base Overflow
HT48R067
Interrupt Source
Priority Vector
RETI
(it will set EMI automatically)
External Interrupt
1
2
04H
08H
0CH
10H
14H
18H
Timer/Event Counter 0 Overflow
Timer/Event Counter 1 Overflow
Timer/Event Counter 2 Overflow
¾
Interrupt Flow
3
4
Interrupt Priority
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In case of simultaneous requests, the
following table shows the priority that is applied. These
can be masked by resetting the EMI bit.
¾
5
Time Base Overflow
In cases where both external and internal interrupts are
enabled and where an external and internal interrupt oc-
curs simultaneously, the external interrupt will always
have priority and will therefore be serviced first. Suitable
masking of the individual interrupts using the interrupt
registers can prevent simultaneous occurrences.
HT48R063/064/065
Interrupt Source
Priority Vector
External Interrupt
1
2
3
04H
08H
0CH
Timer/Event Counter 0 Overflow
Time Base Overflow
Rev. 1.10
53
June 9, 2009
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
