HT48R063/064/065/066/0662/067
plimentary pair PFD and PFD for those devices with
dual outputs.
the Port A control register PAC, to setup the PFD pins as
outputs. If only one pin is setup as an output, the other
pin can still be used as a normal data input pin. How-
ever, if both pins are setup as inputs then the PFD will
not function. For devices with dual outputs the PFD out-
puts will only be activated if bit PA0 is set high. For de-
vices with a single PFD output, bit PA1 must be set high
to activate the PFD. These output data bits can be used
as the on/off control bit for the PFD outputs. Note that
the PFD outputs will all be low if the output data bit is
cleared to zero.
The Timer/Event Counter overflow signal is the clock
source for the PFD function, which is controlled by
PFDCS bit in CTRL0. For applicable devices the clock
source can come from either Timer/Event Counter 0 or
Timer/Event Counter 1. The output frequency is con-
trolled by loading the required values into the timer
prescaler and timer registers to give the required divi-
sion ratio. The counter will begin to count-up from this
preload register value until full, at which point an over-
flow signal is generated, causing both the PFD and PFD
outputs to change state. The counter will then be auto-
matically reloaded with the preload register value and
continue counting-up.
Using this method of frequency generation, and if a
crystal oscillator is used for the system clock, very pre-
cise values of frequency can be generated.
If the CTRL0 register has selected the PFD function,
then for both PFD outputs to operate, it is essential for
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PFD Function - Single Output
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PFD Function
Rev. 1.10
46
June 9, 2009
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
