HT46R068B/HT46R069B
Enhanced A/D Type 8-bit OTP MCU
External Interrupt
For an external interrupt to occur, the global interrupt enable bit, EMI, and external interrupt enable
bit, INTE, must first be set. An actual external interrupt will take place when the external interrupt
request flag, INTF, is set, a situation that will occur when an edge transition appears on the external
INT line. The type of transition that will trigger an external interrupt, whether high to low, low to
high or both is determined by the INTEG0 and INTEG1 bits, which are bits 6 and 7 respectively, in
the CTRL1 control register. These two bits can also disable the external interrupt function.
INTEG1
INTEG0
Edge Trigger Type
Exteꢁnal inteꢁꢁꢀpt disable
Rising edge Tꢁiggeꢁ
Falling edge Tꢁiggeꢁ
Both edge Tꢁiggeꢁ
0
0
1
1
0
1
0
1
The external interrupt pin is pin-shared with the I/O pin PA3 and can only be configured as an
external interrupt pin if the corresponding external interrupt enable bit in the INTC0 register has
been set and the edge trigger type has been selected using the CTRL1 register. The pin must also
be setup as an input by setting the corresponding PAC.3 bit in the port control register. When the
interrupt is enabled, the stack is not full and an active transition appears on the external interrupt
pin, a subroutine call to the external interrupt vector at location 04H, will take place. When the
interrupt is serviced, the external interrupt request flag, EIF, will be automatically reset and the
EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor
connections on this pin will remain valid even if the pin is used as an external interrupt input.
Timer/Event Counter Interrupt
For a Timer/Event Counter interrupt to occur, the global interrupt enable bit, EMI, and the
corresponding timer interrupt enable bit, TnE, must first be set. An actual Timer/Event Counter
interrupt will take place when the Timer/Event Counter request flag, TnF, is set, a situation that will
occur when the relevant Timer/Event Counter overflows. When the interrupt is enabled, the stack
is not full and a Timer/Event Counter n overflow occurs, a subroutine call to the relevant timer
interrupt vector, will take place. When the interrupt is serviced, the timer interrupt request flag, TnF,
will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts.
Multi-function Interrupt
Unlike the other independent interrupts, the Multi-function Interrupt has no independent source,
but rather is formed from other existing interrupt sources, namely the Time-base Interrupt, SIM
Interrupt and SPIA Interrupt. A Multi-function Interrupt request will take place when the Multi-
function Interrupt request flag, MFF is set. The Multi-function Interrupt flag will be set when any
of their included functions generate an interrupt request flag. To allow the program to branch to its
respective interrupt vector address, when the Multi-function Interrupt is enabled and the stack is
not full, and either one of the interrupts contained within each of Multi-function Interrupt occurs,
a subroutine call to the Multi-function Interrupt vector will take place. When the interrupt is
serviced, the Multi-Function Interrupt request flag will be automatically reset and the EMI bit will
be automatically cleared to disable other interrupts. However, it must be noted that, although the
Multi-function Interrupt flag will be automatically reset when the interrupt is serviced, the request
flags from the original source of the Multi-function Interrupt, namely the Time-base Interrupt,
SIM Interrupt and SPIA Interrupt will not be automatically reset and must be manually reset by
the application program. After a Multi-function has been generated, the application program can
determine which interrupt source has occurred by interrogating the interrupt request flags, SIF,
SIMF or TBF within the MFIC register.
Rev. 1.00
7ꢄ
�anꢀaꢁꢂ ꢃꢄꢅ ꢃ011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
