HT46R068B/HT46R069B
Enhanced A/D Type 8-bit OTP MCU
When an interrupt request is generated it takes 2 or 3 instruction cycle before the program jumps
to the interrupt vector. If the device is in the Sleep or Idle Mode and is woken up by an interrupt
request then it will take 3 cycles before the program jumps to the interrupt vector.
Main
Pꢁogꢁam
N
Enable Bit Set ?
Y
Aꢀtomaticallꢂ Disable Inteꢁꢁꢀpt
Main
Cleaꢁ EMI & Reqꢀest Flag
Pꢁogꢁam
Wait foꢁ ꢃ ~ 3 Instꢁꢀction Cꢂcles
ISR Entꢁꢂ
…
…
RETI
(it will set EMI Aꢀtomaticallꢂ)
Interrupt Flow
Interrupt Priority
Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be
serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of
simultaneous requests, the following table shows the priority that is applied. These can be masked
by resetting the EMI bit.
Interrupt Source
Priority
Vector
04H
08H
0CH
10H
14H
Exteꢁnal Inteꢁꢁꢀpt
Timer/Event Counter 0 Overflow
Timer/Event Counter 1 Overflow
Timer/Event Counter 2 Overflow
A/D Inteꢁꢁꢀpt
1
ꢃ
3
4
5
Mꢀlti-fꢀnction Inteꢁꢁꢀpt
(Time Baseꢅ SIMꢅ SPIA)
ꢄ
18H
In cases where both external and internal interrupts are enabled and where an external and internal
interrupt occurs simultaneously, the external interrupt will always have priority and will therefore
be serviced first. Suitable masking of the individual interrupts using the interrupt registers can
prevent simultaneous occurrences.
Rev. 1.00
75
�anꢀaꢁꢂ ꢃꢄꢅ ꢃ011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
